Abstract: The present disclosure provides a voltage generating circuit and a memory. The voltage generating circuit includes: a voltage output module configured to receive a reference voltage, generate a first output voltage, and provide the first output voltage to a power supply node, where the power supply node is connected to a load to supply power to the load; a voltage stabilizing module configured to receive the reference voltage and generate and output a control signal; and a compensation module configured to receive a power voltage, a flag signal and the control signal, be turned on in response to the flag signal, and configured to provide a second output voltage to the power supply node in response to a voltage value of the control signal, such that a voltage of the power supply node is recovered to the first output voltage.

Abstract: The embodiment the disclosure provides a monitoring circuit and a storage system. The monitoring circuit includes a voltage detection module and a logic circuit module. The voltage detection module is configured to output a first detection signal, a second detection signal and a third detection signal through a first node, a second node and a third node, respectively. The logic circuit module is configured to output a monitoring signal through a fourth node; determine whether the first detection signal has a first preset level, whether the second detection signal has a second preset level, and whether the third detection signal has a third preset level, respectively; determine the monitoring signal to be in a valid state in response to the first detection signal having the first preset level, the second detection signal having the second preset level and the third detection signal having the third preset level.

Abstract: A power supply circuit and a chip to which the power supply circuit is applied are disclosed. The power supply circuit includes a constant current generation circuit and a voltage generation circuit. The constant current generation circuit is configured to generate a first current with a positive temperature coefficient and a second current with a negative temperature coefficient, and generate a constant current according to the first current and the second current. The voltage generation circuit includes a transistor, is coupled to the constant current generation circuit, and configured to generate a temperature-dependent voltage according to the constant current and characteristics of the transistor.

Abstract: A power supply circuit and a memory are provided. The power supply circuit includes: a voltage generation module, configured to provide an initial voltage signal; a first power supply module, configured to provide a power reference voltage based on the initial voltage signal; an amplification module, configured to generate and output a first power voltage based on the power reference voltage; a first power network, configured to supply power to at least one function module connected to the first power network; a second power supply module, a second power network and a voltage control module. The second power supply module is configured to provide a second power voltage for the second power network based on the initial voltage signal.

Abstract: The present disclosure provides a delay circuit and a semiconductor device. The delay circuit includes a delay unit and a linear voltage regulator unit; wherein, the delay unit includes an inverting unit and a power supply control unit, and the inverting unit includes an inverting unit and a power supply control unit. The inversion unit receives an input signal and delays the input signal, and the power supply control unit is used for providing a voltage to the inverting unit according to the power supply control signal; the linear voltage stabilization unit is coupled to the delay unit and outputting the power supply control signal according to a reference voltage. The voltage outputs the power control signal. The present disclosure can accurately control the delay time of the delay unit and improve the delay precision of the delay circuit.

Abstract: A bandgap reference circuit includes a feedback transistor, a reference setting circuit, an amplification circuit and an output transistor. A source of the feedback transistor is configured to connect to a first power supply, and a drain of the feedback transistor is configured to connect to a first node. The reference setting circuit includes a first bridge arm and a second bridge arm which are connected in parallel. An inverting input terminal of the amplification circuit is connected to the first bridge arm, and a non-inverting input terminal of the amplification circuit is connected to the second bridge arm. A gate of the output transistor is connected to an output terminal of the amplification circuit, and a source of the output transistor is connected to the first power supply.

Abstract: A drive circuit and a memory chip are provided. The drive circuit includes: an amplification module, working under a first voltage domain; an output module, working under a second voltage domain, a power supply voltage of the second voltage domain being greater than a power supply voltage of the first voltage domain, and an output terminal of the output module being an output terminal of the drive circuit; a connection module, connected to an output terminal of the amplification module and an input terminal of the output module; and a feedback module, an input terminal of the feedback module being connected to the output terminal of the output module, and an output terminal of the feedback module being connected to an input terminal of the amplification module.

Abstract: A bandgap reference circuit includes a feedback transistor, a reference setting circuit, an amplification circuit and an output transistor. A source of the feedback transistor is configured to connect to a first power supply, and a drain of the feedback transistor is configured to connect to a first node. The reference setting circuit includes a first bridge arm and a second bridge arm which are connected in parallel. An inverting input terminal of the amplification circuit is connected to the first bridge arm, and a non-inverting input terminal of the amplification circuit is connected to the second bridge arm. A gate of the output transistor is connected to an output terminal of the amplification circuit, and a source of the output transistor is connected to the first power supply.

Abstract: A clock generation circuit, equidistant four-phase signal generation method and memory are provided. The circuit includes: a four-phase clock generation circuit for receiving an internal clock signal and complementary clock signal of a memory to which the clock generation circuit belongs, configured to generate a first, second, third and fourth clock signals with the same cycle; a signal delay circuit configured to perform signal delay on the first clock signal, second clock signal, third clock signal and fourth clock signal respectively based on the delay command, herein the delays of the first clock signal, second clock signal, third clock signal and fourth clock signal are different; a signal loading circuit configured to generate a first indication signal and second indication signal; and a test circuit configured to perform a duty cycle test based on the first indication signal and second indication signal to acquire equidistant parallel clock signals.

Abstract: The signal generator includes the following: an oscillation generation circuit, configured to generate an initial oscillation signal based on an oscillation control signal; a duty cycle correction circuit, connected to an output end of the oscillation generation circuit and configured to adjust a duty cycle of the initial oscillation signal based on a duty cycle control signal, to generate an adjusted oscillation signal; an output interface, connected to an output end of the duty cycle correction circuit and configured to output the adjusted oscillation signal to an external test system; and an amplitude adjustment circuit, connected to the output end of the duty cycle correction circuit and configured to adjust an amplitude of the adjusted oscillation signal based on an amplitude control signal, to generate a test signal.

Abstract: A test circuit includes first integration circuit configured to receive first test signal and integrate first test signal to output first integrated signal; second integration circuit configured to receive second test signal and integrate second test signal to output second integrated signal, where first test signal and second test signal are signals inverted with respect to each other, value of first integrated signal is product of duty cycle of first test signal and a voltage amplitude of power supply, and value of second integrated signal is product of duty cycle of second test signal and voltage amplitude of power supply; and comparison circuit connected to first and second integration circuits. The comparison circuit is configured to output high-level signal in response to first integrated signal being greater than second integrated signal, and output low-level signal in response to second integrated signal being greater than first integrated signal.

Abstract: A signal detection system and a memory detection method are provided. The system includes a signal generator, generating a reference test signal based on an external parameter, the reference test signal being a clock signal satisfying a preset duty cycle, where a duty cycle test is performed on the reference test signal based on a test circuit, to determine whether a function of the test circuit is normal. If the function of the test circuit is normal, different portions under test are sequentially selected based on a test control signal, and the duty cycle test is performed, based on the test circuit, on a signal outputted by each of the selected portions under test. The portions under test include a signal converter and a write clock path.

Abstract: A comparison circuit includes a comparison module, a state judgment module and a state storage module. The comparison module includes a first input end connected to a voltage to be measured and a second input end connected to a reference voltage. The state judgment module includes a first input end connected to a first output end of the comparison module and a second input end connected to a second output end of the comparison module. The state storage module includes an input end connected to the first output end of the comparison module and an enable end connected to an output end of the state judgment module. The embodiments of the disclosure may improve processing efficiency of the comparison circuit.

Abstract: A drive circuit and a memory chip are provided. The drive circuit includes: an amplification module, working under a first voltage domain; an output module, working under a second voltage domain, a power supply voltage of the second voltage domain being greater than a power supply voltage of the first voltage domain, and an output terminal of the output module being an output terminal of the drive circuit; a connection module, connected to an output terminal of the amplification module and an input terminal of the output module; and a feedback module, an input terminal of the feedback module being connected to the output terminal of the output module, and an output terminal of the feedback module being connected to an input terminal of the amplification module.