Abstract: A method includes providing a first channel layer and a second channel layer over a substrate; forming a first patterned hard mask covering the first channel layer and exposing the second channel layer; selectively depositing a cladding layer on the second channel layer and not on the first patterned hard mask; performing a first thermal drive-in process; removing the first patterned hard mask; after removing the first patterned hard mask, forming an interfacial dielectric layer on the cladding layer and the first channel layer; and forming a high-k dielectric layer on the interfacial dielectric layer.

Abstract: A system performs adaptive thermal ceiling control at runtime. The system includes computing circuits and a thermal management module. When detecting a runtime condition change that affects power consumption in the system, the thermal management module determines an adjustment to the thermal ceiling of a computing circuit, and increases the thermal ceiling of the computing circuit according to the adjustment.

Abstract: A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.

Abstract: The present invention discloses an anti-aging composition, which includes: (a) isolated lactic acid bacterial strains or a fermented product thereof; and (b) an excipient, a diluent, or a carrier; wherein the isolated lactic acid bacterial strains include: Bifidobacterium bifidum VDD088 strains, Bifidobacterium breve Bv-889 strains, and Bifidobacterium longum BLI-02 strains. The present invention further provides a method for preventing aging by administering the foregoing anti-aging composition to a subject in need thereof.

Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, each first semiconductor layer of the one or more first semiconductor layers is surrounded by a first intermixed layer, wherein the first intermixed layer comprises a first material and a second material.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.

Abstract: A Totem Pole PFC circuit includes at least one fast-switching leg, a slow-switching leg, and a control unit. Each fast-switching leg includes a fast-switching upper switch and a fast-switching lower switch. The slow-switching leg is coupled in parallel to the at least one fast-switching leg, and the slow-switching leg includes a slow-switching upper switch and a slow-switching lower switch. The control unit receives an AC voltage with a phase angle, and the control unit includes a current detection loop, a voltage detection loop, and a control loop. The control loop generates a second control signal assembly to respectively control the slow-switching upper switch and the slow-switching lower switch. The control loop controls the second control signal assembly to follow the phase angle, and dynamically adjusts a duty cycle of the second control signal assembly to turn on or turn off the slow-switching upper switch and the slow-switching lower switch.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a dielectric wall adjacent to the first nanostructures. The semiconductor structure also includes a first liner layer between the first nanostructures and the dielectric wall, and the first liner layer is in direct contact with the dielectric wall. The semiconductor structure also includes a gate structure surrounding the first nanostructures, and the first liner layer is in direct contact with a portion of the gate structure.

Abstract: An actuating and sensing module is disclosed and includes a bottom plate, a gas pressure sensor, a thin gas transportation device and a cover plate. The bottom plate includes a pressure relief orifice, a discharging orifice and a communication orifice. The gas pressure sensor is disposed on the bottom plate and seals the communication orifice. The thin gas transportation device is disposed on the bottom plate and seals the pressure relief orifice and the discharging orifice. The cover plate is disposed on the bottom plate and covers the gas pressure sensor and the thin gas-transportation device. The cover plate includes an intake orifice. The thin gas transportation device is driven to inhale gas through the intake orifice, the gas is then discharged through the discharging orifice by the thin gas transportation device, and a pressure change of the gas is sensed by the gas pressure sensor.

Abstract: A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.

Abstract: Crystalline 4-((L-valyl)oxy)butanoic acid, methods of preparing crystalline 4-((L-valyl)oxy)butanoic acid, pharmaceutical compositions of crystalline 4-((L-valyl)oxy)butanoic acid, and methods of treatment using crystalline 4-((L-valyl)oxy)butanoic acid are disclosed.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first channel structure configured to transport charge carriers within a first transistor device and a first gate electrode layer wrapping around the first channel structure. A second channel structure is configured to transport charge carriers within a second transistor device. A second gate electrode layer wraps around the second channel structure. The second gate electrode layer continuously extends from around the second channel structure to cover the first gate electrode layer. A third channel structure is configured to transport charge carriers within a third transistor device. A third gate electrode layer wraps around the third channel structure. The third gate electrode layer continuously extends from around the third channel structure to cover the second gate electrode layer.

Abstract: Disclosed herein is a probiotic composition that includes Lactobacillus salivarius subsp. salicinius AP-32, Lactobacillus johnsonii MH-68, and Bifidobacterium animalis subsp. lactis CP-9, which are deposited at the China Center for Type Culture Collection (CCTCC) respectively under accession numbers CCTCC M 2011127, CCTCC M 2011128, and CCTCC M 2014588. A number ratio of Lactobacillus salivarius subsp. salicinius AP-32, Lactobacillus johnsonii MH-68, and Bifidobacterium animalis subsp. lactis CP-9 ranges from 1:0.1:0.1 to 1:1:8. Also disclosed herein is use of the probiotic composition for alleviating type 1 diabetes mellitus (T1DM).

Abstract: Test equipment for a battery management system is provided. A battery-parameter recognition module measures a standard battery to obtain the first correction input, and uses the capacity test formula and the relaxation time test formula to perform a first charge and discharge test on the battery to be tested to obtain first battery parameter. A real-time simulation module determines the battery model and the simulated battery state based on the first battery parameter and the dynamic load. Each simulator of a physical signal simulation module provides a battery physical signal indicating the battery model. A connector provides the battery physical signal to the battery management controller under test. The battery management controller under test provides a stimulated battery state based on the battery physical signal. Master equipment compares the simulated battery state with an estimated battery state to determine whether the battery management controller under test is normal.

Abstract: A transferring apparatus configured to transfer an electronic component includes a first carrier, a second carrier, an actuator mechanism, and a flexible push generator. The first carrier is configured to carry an objective substrate, and the second carrier is configured to carry a transfer substrate. The actuator mechanism is configured to actuate the first carrier and the second carrier to move close to and away from each other. The flexible push generator is disposed near the first carrier or the second carrier and generates a flexible push to the carried objective substrate or transfer substrate when the first carrier and the second carrier are actuated in a way close to each other. A method of bonding an electronic component and a method for manufacturing a light-emitting diode display are also provided.

Abstract: Test equipment for a battery management system is provided. A battery-parameter recognition module measures a standard battery to obtain the first correction input, and uses the capacity test formula and the relaxation time test formula to perform a first charge and discharge test on the battery to be tested to obtain first battery parameter. A real-time simulation module determines the battery model and the simulated battery state based on the first battery parameter and the dynamic load. Each simulator of a physical signal simulation module provides a battery physical signal indicating the battery model. A connector provides the battery physical signal to the battery management controller under test. The battery management controller under test provides a stimulated battery state based on the battery physical signal. Master equipment compares the simulated battery state with an estimated battery state to determine whether the battery management controller under test is normal.

Abstract: An anti-theft control method for a vehicle comprises determining whether an enabling signal is received by a control device in an anti-theft mode; performing an anti-theft control process by the control device when receiving the enabling signal, wherein the anti-theft control process comprising: detecting a set of position information related to the motor by a position sensor; generating an anti-theft control command according to the set of position information and further outputting a plurality of switching control instructions according to the anti-theft control command by the control device; and outputting a locking command to the motor by a power driving device according to the plurality of switching control instructions for driving the motor to generate a braking force. The locking command comprises a plurality of PWM signals, with one of the plurality of PWM signals has two adjacent periods having the same duty ratio.

Abstract: This invention discloses a lead-free Sn—Zn—Al—Ag solder alloy, which is composed of 7-10 wt % of Zn, up to 0.5 wt % of Al, up to 4.0 wt % of Ag, and the balance of Sn; and a lead-free Sn—Zn—Al—Ag—Ga solder alloy, which is composed of 7-10 wt % of Zn, up to 0.5 wt % of Al, up to 4.0 wt % of Ag, up to 4.0 wt % of Ga; and the balance of Sn. The lead-free solder alloys of the present invention have better tensile strength and elongation than the conventional Sn—Pb solder alloys. In addition, the lead-free solder alloys of the present invention have a melting point lower than 200° C., which is close to the 183.5° C. of an eutectic Sn—Pb alloy.

Abstract: This invention discloses a lead-free Sn—Zn—Al—Ag solder alloy, which is composed of 7-10 wt % of Zn, up to 0.5 wt % of Al, up to 4.0 wt % of Ag, and the balance of Sn; and a lead-free Sn—Zn—Al—Ag—Ga solder alloy, which is composed of 7-10 wt % of Zn, up to 0.5 wt % of Al, up to 4.0 wt % of Ag, up to 4.0 wt % of Ga; and the balance of Sn. The lead-free solder alloys of the present invention have better tensile strength and elongation than the conventional Sn—Pb solder alloys. In addition, the lead-free solder alloys of the present invention have a melting point lower than 200° C., which is close to the 183.5° C. of an eutectic Sn—Pb alloy.