Patents by Inventor Jie-Cheng Deng
Jie-Cheng Deng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11776880Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. A surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.Type: GrantFiled: October 19, 2020Date of Patent: October 3, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Horng Chang, Jie-Cheng Deng, Tin-Hao Kuo, Ying-Yu Chen
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Publication number: 20220172997Abstract: A semiconductor structure includes a first fin, a second fin, a first gate, a second gate, at least one spacer, and an insulating structure. The first gate is present on the first fin. The second gate is present on the second fin. The spacer is present on at least one side wall of at least one of the first gate and the second gate. The insulating structure is present between the first fin and the second fin, in which the spacer is substantially absent between the insulating structure and said at least one of the first gate and the second gate.Type: ApplicationFiled: February 14, 2022Publication date: June 2, 2022Inventors: Jie-Cheng Deng, Horng-Huei Tseng, Yi-Jen Chen
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Patent number: 11251085Abstract: A semiconductor structure includes a first fin, a second fin, a first gate, a second gate, at least one spacer, and an insulating structure. The first gate is present on the first fin. The second gate is present on the second fin. The spacer is present on at least one side wall of at least one of the first gate and the second gate. The insulating structure is present between the first fin and the second fin, in which the spacer is substantially absent between the insulating structure and said at least one of the first gate and the second gate.Type: GrantFiled: July 31, 2018Date of Patent: February 15, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jie-Cheng Deng, Horng-Huei Tseng, Yi-Jen Chen
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Patent number: 10943977Abstract: A semiconductor device is disclosed. The semiconductor device includes a channel region, extending along a direction, that has a U-shaped cross-section; a gate dielectric layer wrapping around the channel region; and a gate electrode wrapping around respective central portions of the gate dielectric layer and the channel region.Type: GrantFiled: December 11, 2019Date of Patent: March 9, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jie-Cheng Deng, Yi-Jen Chen, Chia-Yang Liao
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Publication number: 20210050281Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. A surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.Type: ApplicationFiled: October 19, 2020Publication date: February 18, 2021Inventors: Chih-Horng Chang, Jie-Cheng Deng, Tin-Hao Kuo, Ying-Yu Chen
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Patent number: 10811338Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. A surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.Type: GrantFiled: December 17, 2019Date of Patent: October 20, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Horng Chang, Jie-Cheng Deng, Tin-Hao Kuo, Ying-Yu Chen
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Publication number: 20200126893Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. A surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.Type: ApplicationFiled: December 17, 2019Publication date: April 23, 2020Inventors: Chih-Horng Chang, Jie-Cheng Deng, Tin-Hao Kuo, Ying-Yu Chen
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Publication number: 20200111873Abstract: A semiconductor device is disclosed. The semiconductor device includes a channel region, extending along a direction, that has a U-shaped cross-section; a gate dielectric layer wrapping around the channel region; and a gate electrode wrapping around respective central portions of the gate dielectric layer and the channel region.Type: ApplicationFiled: December 11, 2019Publication date: April 9, 2020Inventors: Jie-Cheng Deng, Yi-Jen Chen, Chia-Yang Liao
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Patent number: 10522444Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. In an embodiment, a surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.Type: GrantFiled: May 15, 2013Date of Patent: December 31, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Horng Chang, Jie-Cheng Deng, Tin-Hao Kuo, Ying-Yu Chen
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Patent number: 10510840Abstract: A semiconductor device is disclosed. The semiconductor device includes a channel region, extending along a direction, that has a U-shaped cross-section; a gate dielectric layer wrapping around the channel region; and a gate electrode wrapping around respective central portions of the gate dielectric layer and the channel region.Type: GrantFiled: June 20, 2017Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jie-Cheng Deng, Yi-Jen Chen, Chia-Yang Liao
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Patent number: 10510608Abstract: A semiconductor structure includes a first fin, a second fin, a first gate, a second gate, at least one spacer, and an insulating structure. The first gate is present on the first fin. The second gate is present on the second fin. The spacer is present on at least one side wall of at least one of the first gate and the second gate. The insulating structure is present between the first fin and the second fin, in which the spacer is substantially absent between the insulating structure and said at least one of the first gate and the second gate.Type: GrantFiled: March 4, 2016Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jie-Cheng Deng, Horng-Huei Tseng, Yi-Jen Chen
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Publication number: 20180366545Abstract: A semiconductor device is disclosed. The semiconductor device includes a channel region, extending along a direction, that has a U-shaped cross-section; a gate dielectric layer wrapping around the channel region; and a gate electrode wrapping around respective central portions of the gate dielectric layer and the channel region.Type: ApplicationFiled: June 20, 2017Publication date: December 20, 2018Inventors: Jie-Cheng DENG, Yi-Jen Chen, Chia-Yang Liao
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Publication number: 20180350692Abstract: A semiconductor structure includes a first fin, a second fin, a first gate, a second gate, at least one spacer, and an insulating structure. The first gate is present on the first fin. The second gate is present on the second fin. The spacer is present on at least one side wall of at least one of the first gate and the second gate. The insulating structure is present between the first fin and the second fin, in which the spacer is substantially absent between the insulating structure and said at least one of the first gate and the second gate.Type: ApplicationFiled: July 31, 2018Publication date: December 6, 2018Inventors: Jie-Cheng Deng, Horng-Huei Tseng, Yi-Jen Chen
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Patent number: 9947592Abstract: FinFET devices and methods of forming the same are disclosed. One of the FinFET devices includes a substrate, multiple gates and a single spacer wall. The substrate is provided with multiple fins extending in a first direction. The multiple gates extending in a second direction different from the first direction are provided respectively across the fins. Two of the adjacent gates are arranged end to end. The single spacer wall extending in the first direction is located between the facing ends of the adjacent gates and is in physical contact with a gate dielectric material of each of the adjacent gates.Type: GrantFiled: November 16, 2015Date of Patent: April 17, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jie-Cheng Deng, Yi-Jen Chen, Horng-Huei Tseng
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Publication number: 20170256457Abstract: A semiconductor structure includes a first fin, a second fin, a first gate, a second gate, at least one spacer, and an insulating structure. The first gate is present on the first fin. The second gate is present on the second fin. The spacer is present on at least one side wall of at least one of the first gate and the second gate. The insulating structure is present between the first fin and the second fin, in which the spacer is substantially absent between the insulating structure and said at least one of the first gate and the second gate.Type: ApplicationFiled: March 4, 2016Publication date: September 7, 2017Inventors: Jie-Cheng DENG, Horng-Huei TSENG, Yi-Jen CHEN
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Publication number: 20170141111Abstract: FinFET devices and methods of forming the same are disclosed. One of the FinFET devices includes a substrate, multiple gates and a single spacer wall. The substrate is provided with multiple fins extending in a first direction. The multiple gates extending in a second direction different from the first direction are provided respectively across the fins. Two of the adjacent gates are arranged end to end. The single spacer wall extending in the first direction is located between the facing ends of the adjacent gates and is in physical contact with a gate dielectric material of each of the adjacent gates.Type: ApplicationFiled: November 16, 2015Publication date: May 18, 2017Inventors: Jie-Cheng Deng, Yi-Jen Chen, Horng-Huei Tseng
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Patent number: 9601492Abstract: FinFET devices and methods of forming the same are disclosed. One of the FinFET devices includes a substrate, multiple gates and an insulating wall. The substrate is provided with multiple fins extending in a first direction. The multiple gates extending in a second direction different from the first direction are provided respectively across the fins. Two of the adjacent gates are arranged end to end. The insulating wall extending in the first direction is located between the facing ends of the adjacent gates and is in physical contact with a gate dielectric material of each of the adjacent gates.Type: GrantFiled: November 16, 2015Date of Patent: March 21, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jie-Cheng Deng, Yi-Jen Chen, Horng-Huei Tseng
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Publication number: 20140252614Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. In an embodiment, a surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.Type: ApplicationFiled: May 15, 2013Publication date: September 11, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Horng Chang, Jie-Cheng Deng, Tin-Hao Kuo, Ying-Yu Chen
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Publication number: 20100116462Abstract: A heat dissipation system comprises a printed circuit board and at least a heat dissipation device mounted on the printed circuit board for dissipating heat generated by an electronic member mounted on the printed circuit board. The at least a heat dissipation device comprises a base, a plurality of fins extending upwardly from the base and an air guiding member located at a corner of the base. These fins are spaced from each other to define a plurality of heat exchange passages. Non-fins are disposed at a side of the base to define a cooling air passage. The cooling air passage is parallel to the heat exchange passages of the fins. The air guiding member is located in the cooling air passage for controlling open and close of the cooling air passage.Type: ApplicationFiled: April 29, 2009Publication date: May 13, 2010Applicants: FU ZHUN PRECISION INDUSTRY (SHEN ZHEN) CO., LTD., FOXCONN TECHNOLOGY CO., LTD.Inventors: MENG FU, JIE-CHENG DENG, CHUN-CHI CHEN
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Patent number: 7633755Abstract: A heat dissipation device assembly for dissipating heat from a plurality of electronic components mounted on a printed circuit board, includes a heat sink (10) contacting one of the electronic components, a pair of fans (20) attached on a lateral side of the heat sink, and a fan duct (30) fixed on the fans. A plurality of guiding members (322, 346) are formed inwardly from the fan duct to be located in an interior of the fan duct. The guiding members are used for guiding a screwdriver (40) to accurately fit with screws (50) preassembled to the heat sink. Thus, the screws can be quickly and easily fastened by the screwdriver to mount the heat dissipation device assembly on the printed circuit board.Type: GrantFiled: November 15, 2007Date of Patent: December 15, 2009Assignees: Fu Zhun Precision Industry (Shen Zhen) Co., Ltd., Foxconn Technology Co., Ltd.Inventors: Shi-Wen Zhou, Jun Cao, Jie-Cheng Deng