Patents by Inventor Jie Jason Sun

Jie Jason Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Three dimensional NAND flash with self-aligned select gate
    Patent number: 10229928
    Abstract: An integrated circuit may include a pillar of semiconductor material, a field effect transistor having a channel that is formed in the pillar of semiconductor material, and two or more memory cells, stacked vertically on top of the field effect transistor, and having channels that are formed in the pillar semiconductor of material.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: March 12, 2019
    Assignee: Intel Corporation
    Inventors: Jie Jason Sun, Brian Cleereman, Minsoo Lee
  • THREE DIMENSIONAL NAND FLASH WITH SELF-ALIGNED SELECT GATE
    Publication number: 20160307914
    Abstract: An integrated circuit may include a pillar of semiconductor material, a field effect transistor having a channel that is formed in the pillar of semiconductor material, and two or more memory cells, stacked vertically on top of the field effect transistor, and having channels that are formed in the pillar semiconductor of material.
    Type: Application
    Filed: April 19, 2016
    Publication date: October 20, 2016
    Inventors: Jie Jason Sun, Brian Cleereman, Minsoo Lee
  • Stacked thin channels for boost and leakage improvement
    Patent number: 9412821
    Abstract: A hollow-channel memory device comprises a source layer, a first hollow-channel pillar structure formed on the source layer, and a second hollow-channel pillar structure formed on the first hollow-channel pillar structure. The first hollow-channel pillar structure comprises a first thin channel and the second hollow-channel pillar structure comprises a second thin channel that is in contact with the first thin channel. In one exemplary embodiment, the first thin channel comprises a first level of doping; and the second thin channel comprises a second level of doping that is different from the first level of doping. In another exemplary embodiment, the first and second levels of doping are the same.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: August 9, 2016
    Assignee: Intel Corporation
    Inventors: Fatma Arzum Simsek-Ege, Jie Jason Sun, Benben Li, Srikant Jayanti, Han Zhao, Guangyu Huang, Haitao Liu
  • STACKED THIN CHANNELS FOR BOOST AND LEAKAGE IMPROVEMENT
    Publication number: 20160126311
    Abstract: A hollow-channel memory device comprises a source layer, a first hollow-channel pillar structure formed on the source layer, and a second hollow-channel pillar structure formed on the first hollow-channel pillar structure. The first hollow-channel pillar structure comprises a first thin channel and the second hollow-channel pillar structure comprises a second thin channel that is in contact with the first thin channel. In one exemplary embodiment, the first thin channel comprises a first level of doping; and the second thin channel comprises a second level of doping that is different from the first level of doping. In another exemplary embodiment, the first and second levels of doping are the same.
    Type: Application
    Filed: November 5, 2015
    Publication date: May 5, 2016
    Applicant: Intel Corporation
    Inventors: Fatma Arzum Simsek-Ege, Jie Jason Sun, Benben Li, Srikant Jayanti, Han Zhao, Guangyu Huang, Haitao Liu
  • Stacked thin channels for boost and leakage improvement
    Patent number: 9209199
    Abstract: A hollow-channel memory device comprises a source layer, a first hollow-channel pillar structure formed on the source layer, and a second hollow-channel pillar structure formed on the first hollow-channel pillar structure. The first hollow-channel pillar structure comprises a first thin channel and the second hollow-channel pillar structure comprises a second thin channel that is in contact with the first thin channel. In one exemplary embodiment, the first thin channel comprises a first level of doping; and the second thin channel comprises a second level of doping that is different from the first level of doping. In another exemplary embodiment, the first and second levels of doping are the same.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: December 8, 2015
    Assignee: Intel Corporation
    Inventors: Fatma Arzum Simsek-Ege, Jie Jason Sun, Benben Li, Srikant Jayanti, Han Zhao, Guangyu Huang, Haitao Liu
  • STACKED THIN CHANNELS FOR BOOST AND LEAKAGE IMPROVEMENT
    Publication number: 20150270280
    Abstract: A hollow-channel memory device comprises a source layer, a first hollow-channel pillar structure formed on the source layer, and a second hollow-channel pillar structure formed on the first hollow-channel pillar structure. The first hollow-channel pillar structure comprises a first thin channel and the second hollow-channel pillar structure comprises a second thin channel that is in contact with the first thin channel. In one exemplary embodiment, the first thin channel comprises a first level of doping; and the second thin channel comprises a second level of doping that is different from the first level of doping. In another exemplary embodiment, the first and second levels of doping are the same.
    Type: Application
    Filed: March 21, 2014
    Publication date: September 24, 2015
    Inventors: Fatma Arzum Simsek-Ege, Jie Jason Sun, Benben Li, Srikant Jayanti