Abstract: A method for forming a protection diode utilizes processing operations and materials used in the formation of the CMOS integrated circuit device and provides a protection diode used in CMOS integrated circuit devices to direct charged particles to benign locations and prevent damage to the devices. The protection diode includes a well region of a first conductivity type formed in a surface of a semiconductor substrate, a heavily doped P-type impurity region disposed within the well region, a heavily doped N-type impurity region disposed within the well region and an STI structure interposed therebetween. A top surface of the STI structure extends above the surface. A silicide resistant block-out layer is formed over the STI structure and extends laterally beyond the STI structure, covering any counterdoped sections that may undesirably be formed in the substrate adjacent the STI structure during implantation operations.

Abstract: A method for forming a protection diode utilizes processing operations and materials used in the formation of the CMOS integrated circuit device and provides a protection diode used in CMOS integrated circuit devices to direct charged particles to benign locations and prevent damage to the devices. The protection diode includes a well region of a first conductivity type formed in a surface of a semiconductor substrate, a heavily doped P-type impurity region disposed within the well region, a heavily doped N-type impurity region disposed within the well region and an STI structure interposed therebetween. A top surface of the STI structure extends above the surface. A silicide resistant block-out layer is formed over the STI structure and extends laterally beyond the STI structure, covering any counterdoped sections that may undesirably be formed in the substrate adjacent the STI structure during implantation operations.

Abstract: A protection diode is used in a CMOS integrated circuit device to direct charged particles to benign locations and prevent damage to the device. The protection diode includes a well region of a first conductivity type formed in a surface of a semiconductor substrate, a heavily doped P-type impurity region disposed within the well region, a heavily doped N-type impurity region disposed within the well region and an STI structure interposed therebetween. A top surface of the STI structure extends above the surface. A silicide resistant block-out layer is formed over the STI structure and extends laterally beyond the STI structure, covering any counterdoped sections that may undesirably be formed in the substrate adjacent the STI structure during implantation operations. The method for forming the structure utilizes processing operations and materials used in the formation of the CMOS integrated circuit device.

Abstract: A protection diode is used in a CMOS integrated circuit device to direct charged particles to benign locations and prevent damage to the device. The protection diode includes a well region of a first conductivity type formed in a surface of a semiconductor substrate, a heavily doped P-type impurity region disposed within the well region, a heavily doped N-type impurity region disposed within the well region and an STI structure interposed therebetween. A top surface of the STI structure extends above the surface. A silicide resistant block-out layer is formed over the STI structure and extends laterally beyond the STI structure, covering any counterdoped sections that may undesirably be formed in the substrate adjacent the STI structure during implantation operations. The method for forming the structure utilizes processing operations and materials used in the formation of the CMOS integrated circuit device.

Abstract: A high-voltage transistor device with an interlayer dielectric (ILD) etch stop layer for use in a subsequent contact hole process is provided. The etch stop layer is a high-resistivity film having a resistivity greater than 10 ohm-cm, thus leakage is prevented and breakdown voltage is improved when driving a high voltage greater than 5V at the gate site. A method for fabricating the high-voltage device is compatible with current low-voltage device processes and middle-voltage device processes.

Abstract: A method of forming an interconnect or metal line in a semiconductor device using an zinc activated metal surface and electroless deposition. The invention forms an active metal layer (e.g., Al) layer on an insulating layer in a via hole, activates the active metal layer to form a Zn layer, and electrolessly deposits a metal (e.g., Cu, Ni, Au, or Ag) by reacting with the Zn layer. The metal layer is electroless deposited over the insulating layer. The metal layer fills the via hole to form a metal interconnect or line. Key features of the invention are the active metal layer and the zincate process (not a zinc particle process).

Abstract: A new method of recycling a spin-on-glass control wafer by removing spin-on-glass residue from the control wafer surface is described. A silicon control wafer is provided having a spin-on-glass layer coated thereon. The spin-on-glass layer is removed using a hydrofluoric acid dip wherein a silk-like spin-on-glass residue 15 remains on the silicon control wafer surface. The silicon control wafer surface is cleaned with a Caro's dip whereby the spin-on-glass residue is removed. Thereafter, the silicon control wafer can be reused.

Abstract: The present invention relates to a fluoroborate solder electroplating solution containing lead (Pb) and tin (Sn) ions, in which the total Pb and Sn ion content is 35.5 to 150 g/l, and 70 wt % of them is Sn. The fluoroborate solder electroplating solution further contains 0.05-5 g gelatin per liter of the solder electroplating solution as an additive for increasing the deposition of Sn ions and enhancing the microstructural fineness of the solder plating. A suitable current density is 1 to 3 A/dm.sup.2 in electroplating the present solder electroplating solution.