Abstract: A power measurement system is disclosed for use on an integrated circuit for measuring the power used by the integrated circuit. The power measurement system includes a low-dropout voltage regulator and a signal input unit. The low-dropout voltage regulator includes a power transistor that couples a supply voltage to a circuit to be powered by the supply voltage, and the low-dropout voltage regulator provides an internal adjustment signal (Vsen) for adjusting the internal resistance of the power transistor. The signal input unit receives the internal adjustment signal (Vsen) and provides a power measurement signal responsive to the internal adjustment signal (Vsen).

Abstract: A power measurement system is disclosed for use on an integrated circuit for measuring the power used by the integrated circuit. The power measurement system includes a low-dropout voltage regulator and a signal input unit. The low-dropout voltage regulator includes a power transistor that couples a supply voltage to a circuit to be powered by the supply voltage, and the low-dropout voltage regulator provides an internal adjustment signal (Vsen) for adjusting the internal resistance of the power transistor. The signal input unit receives the internal adjustment signal (Vsen) and provides a power measurement signal responsive to the internal adjustment signal (Vsen).

Abstract: A power measurement system is disclosed for use on an integrated circuit for measuring the power used by the integrated circuit. The power measurement system includes a low-dropout voltage regulator and a signal input unit. The low-dropout voltage regulator includes a power transistor that couples a supply voltage to a circuit to be powered by the supply voltage, and the low-dropout voltage regulator provides an internal adjustment signal (Vsen) for adjusting the internal resistance of the power transistor. The signal input unit receives the internal adjustment signal (Vsen) and provides a power measurement signal responsive to the internal adjustment signal (Vsen).

Abstract: A programmable jitter signal generator is provided that includes a jitter distribution control unit, a selection unit in signal communication with the jitter distribution control unit, and a delay unit in signal communication with the selection unit; and a corresponding method of generating a programmable jitter signal includes programming a control unit, receiving a reference signal, delaying the received reference signal by a multiple of a base time increment, and selecting a delayed reference signal delayed by a desired multiple of the base time increment in accordance with the programmed control unit.

Abstract: A programmable jitter signal generator is provided that includes a jitter distribution control unit, a selection unit in signal communication with the jitter distribution control unit, and a delay unit in signal communication with the selection unit; and a corresponding method of generating a programmable jitter signal includes programming a control unit, receiving a reference signal, delaying the received reference signal by a multiple of a base time increment, and selecting a delayed reference signal delayed by a desired multiple of the base time increment in accordance with the programmed control unit.

Abstract: A system for correcting a single bit error and detecting burst errors is provided. A check bit generator generates partition check bits and burst check bits based on a H-parity matrix data regeneration scheme which provides an a single error correction and multiple bit error detection code which is linear and has the property of self orthogonality within a subclass of self orthogonal codes exclusive of Latin square codes. These check bits provide two independent sources for ascertaining the correct value for any given data bit. An error corrector and detector takes as input the data bits and check bits and provides a corrected data bit output as well as a set of error status lines. The error corrector and detector consists of Error Corrector, error corrector/detector and Error Status modules.