Patents by Inventor Jieyao Liu
Jieyao Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11979150Abstract: A leakage compensation dynamic register, a data operation unit, a chip, a hash board, and a computing apparatus. The leakage compensation dynamic register comprises: an input terminal, an output terminal, a clock signal terminal, and an analog switch unit; a data latch unit for latching the data under control of the clock signal; and an output drive unit for inverting and outputting the data received from the data latch unit, the analog switch unit, the data latch unit, and the output drive unit being sequentially connected in series between the input terminal and the output terminal, and the analog switch unit and the data latch unit having a node therebetween, wherein the leakage compensation dynamic register further comprises a leakage compensation unit electrically connected between the node and the output terminal.Type: GrantFiled: June 29, 2020Date of Patent: May 7, 2024Assignee: Hangzhou Canaan Intelligence Information Technology Co, LtdInventors: Jian Zhang, Nangeng Zhang, Jinhua Bao, Jieyao Liu, Jingjie Wu, Shenghou Ma
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Patent number: 11799456Abstract: A clock generation circuit, a latch using same, and a computing device are provided. The clock generation circuit includes an input end, configured to input a pulse signal; a first output end, configured to output a first clock signal; a second output end, configured to output a second clock signal; and an input drive circuit, a latch circuit, an edge shaping circuit, a feedback delay circuit, and an output drive circuit, where the input drive circuit, the latch circuit, the edge shaping circuit, the feedback delay circuit, and the output drive circuit are sequentially connected between the input end and the first output end as well as the second output end in series. A clock pulse can be effectively shaped, the use of a clock buffer can be reduced, and the correctness and accuracy of data transmission and latching can be improved.Type: GrantFiled: June 30, 2022Date of Patent: October 24, 2023Assignee: Canaan Creative (SH) Co., LTD.Inventors: Jieyao Liu, Nangeng Zhang, Jingjie Wu, Shenghou Ma
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Publication number: 20220345133Abstract: A leakage compensation dynamic register, a data operation unit, a chip, a hash board, and a computing apparatus. The leakage compensation dynamic register comprises: an input terminal, an output terminal, a clock signal terminal, and an analog switch unit; a data latch unit for latching the data under control of the clock signal; and an output drive unit for inverting and outputting the data received from the data latch unit, the analog switch unit, the data latch unit, and the output drive unit being sequentially connected in series between the input terminal and the output terminal, and the analog switch unit and the data latch unit having a node therebetween, wherein the leakage compensation dynamic register further comprises a leakage compensation unit electrically connected between the node and the output terminal.Type: ApplicationFiled: June 29, 2020Publication date: October 27, 2022Applicant: Hangzhou Canaan Intelligence Information Technology Co, LtdInventors: Jian ZHANG, Nangeng ZHANG, Jinhua BAO, Jieyao LIU, Jingjie WU, Shenghou MA
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Publication number: 20220337229Abstract: A clock generation circuit, a latch using same, and a computing device are provided. The clock generation circuit includes an input end, configured to input a pulse signal; a first output end, configured to output a first clock signal; a second output end, configured to output a second clock signal; and an input drive circuit, a latch circuit, an edge shaping circuit, a feedback delay circuit, and an output drive circuit, where the input drive circuit, the latch circuit, the edge shaping circuit, the feedback delay circuit, and the output drive circuit are sequentially connected between the input end and the first output end as well as the second output end in series. A clock pulse can be effectively shaped, the use of a clock buffer can be reduced, and the correctness and accuracy of data transmission and latching can be improved.Type: ApplicationFiled: June 30, 2022Publication date: October 20, 2022Inventors: Jieyao LIU, Nangeng ZHANG, Jingjie WU, Shenghou MA
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Patent number: 11442517Abstract: The invention provides an on-chip passive power supply compensation circuit, and an operational unit, a chip, a hash board and a computing device using the same. The on-chip passive power supply compensation circuit comprises: two or more to-be-powered voltage domains, wherein the to-be-powered voltage domains are connected in series between a power supply and ground; and two or more isolation regions, wherein the to-be-powered voltage domains are formed in the isolation regions, and the isolation regions are configured for isolating the to-be-powered voltage domains; the isolation regions are connected in series between the power supply and the ground, wherein the on-chip passive power supply compensation circuit further comprises power supply compensation units connected between the to-be-powered voltage domains and the isolation regions for providing power supply compensation to the to-be-powered voltage domains.Type: GrantFiled: June 6, 2019Date of Patent: September 13, 2022Assignee: CANAAN CREATIVE CO., LTD.Inventors: Jieyao Liu, Nangeng Zhang, Jingjie Wu, Shenghou Ma
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Patent number: 11409314Abstract: The invention provides a full swing voltage conversion circuit. The full swing voltage conversion circuit comprises: an input terminal for inputting a first level signal; an output terminal for outputting a second level signal; a differential input unit for inverting the first level signal of the input terminal, and outputting a differential input signal; a conversion unit; and an output driving unit; wherein the full swing voltage conversion circuit further comprises an auxiliary pull-down unit between the input terminal and the conversion unit for receiving a feedback to improve capability of the conversion unit in recognizing the differential input signal, such that the full swing voltage conversion circuit of the invention can convert from inputting a low voltage to outputting a high voltage.Type: GrantFiled: May 7, 2019Date of Patent: August 9, 2022Assignee: CANAAN CREATIVE CO., LTD.Inventors: Jieyao Liu, Nangeng Zhang, Jingjie Wu, Shenghou Ma
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Publication number: 20220116027Abstract: The invention provides a dynamic D flip-flop, and a data operation unit, a chip, a hash board and a computing device using the same. The dynamic D flip-flop comprises: an input terminal, an output terminal and at least one clock signal terminal; a latch unit for latching data of the input terminal and inversely transmitting the data under control of a clock signal; and an output driving unit for inverting and outputting the data received from the latch unit; wherein the latch unit outputs in high level, low level and high impedance states by means of a single element under control of a clock signal. Therefore, the invention can effectively reduce chip area, power consumption, and logic delay.Type: ApplicationFiled: December 23, 2021Publication date: April 14, 2022Applicant: CANAAN CREATIVE CO., LTD.Inventors: Jieyao LIU, Nangeng ZHANG, Jingjie WU, Shenghou MA
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Patent number: 11251781Abstract: The invention provides a dynamic D flip-flop, and a data operation unit, a chip, a hash board and a computing device using the same. The dynamic D flip-flop comprises: an input terminal, an output terminal and at least one clock signal terminal; a first latch unit for transmitting data of the input terminal and latching the data under control of a clock signal; a second latch unit for latching data of the output terminal and inversely transmitting the data latched by the first latch unit under control of a clock signal; and an output driving unit for inverting and outputting the data received from the second latch unit; wherein the second latch unit outputs in high level, low level and high impedance states by means of a single element under control of a clock signal. Therefore, the invention can effectively reduce chip area, power consumption, and logic delay.Type: GrantFiled: May 7, 2019Date of Patent: February 15, 2022Assignee: CANAAN CREATIVE CO., LTD.Inventors: Jieyao Liu, Nangeng Zhang, Jingjie Wu, Shenghou Ma
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Publication number: 20210405673Abstract: The invention provides a full swing voltage conversion circuit. The full swing voltage conversion circuit comprises: an input terminal for inputting a first level signal; an output terminal for outputting a second level signal; a differential input unit for inverting the first level signal of the input terminal, and outputting a differential input signal; a conversion unit; and an output driving unit; wherein the full swing voltage conversion circuit further comprises an auxiliary pull-down unit between the input terminal and the conversion unit for receiving a feedback to improve capability of the conversion unit in recognizing the differential input signal, such that the full swing voltage conversion circuit of the invention can convert from inputting a low voltage to outputting a high voltage.Type: ApplicationFiled: May 7, 2019Publication date: December 30, 2021Inventors: Jieyao Liu, Nangeng Zhang, Jingjie Wu, Shenghou Ma
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Publication number: 20210263575Abstract: The invention provides an on-chip passive power supply compensation circuit, and an operational unit, a chip, a hash board and a computing device using the same. The on-chip passive power supply compensation circuit comprises: two or more to-be-powered voltage domains, wherein the to-be-powered voltage domains are connected in series between a power supply and ground; and two or more isolation regions, wherein the to-be-powered voltage domains are formed in the isolation regions, and the isolation regions are configured for isolating the to-be-powered voltage domains; the isolation regions are connected in series between the power supply and the ground, wherein the on-chip passive power supply compensation circuit further comprises power supply compensation units connected between the to-be-powered voltage domains and the isolation regions for providing power supply compensation to the to-be-powered voltage domains.Type: ApplicationFiled: June 6, 2019Publication date: August 26, 2021Inventors: Jieyao Liu, Nangeng Zhang, Jingjie Wu, Shenghou Ma
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Publication number: 20210167761Abstract: The invention provides a dynamic D flip-flop, and a data operation unit, a chip, a hash board and a computing device using the same. The dynamic D flip-flop comprises: an input terminal, an output terminal and at least one clock signal terminal; a first latch unit for transmitting data of the input terminal and latching the data under control of a clock signal; a second latch unit for latching data of the output terminal and inversely transmitting the data latched by the first latch unit under control of a clock signal; and an output driving unit for inverting and outputting the data received from the second latch unit; wherein the second latch unit outputs in high level, low level and high impedance states by means of a single element under control of a clock signal. Therefore, the invention can effectively reduce chip area, power consumption, and logic delay.Type: ApplicationFiled: May 7, 2019Publication date: June 3, 2021Inventors: Jieyao LIU, Nangeng ZHANG, Jingjie WU, Shenghou MA
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Patent number: 10446233Abstract: The present disclosure relates to a structure which includes a self-referenced multiplexer circuit which is configured to pre-charge a plurality of sense lines to a voltage threshold in a first time period and sense and detect a value of a selected sense line of the sense lines in a second time period.Type: GrantFiled: August 23, 2017Date of Patent: October 15, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Igor Arsovski, Qing Li, Xiaoli Hu, Wei Zhao, Jieyao Liu
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Publication number: 20190066786Abstract: The present disclosure relates to a structure which includes a self-referenced multiplexer circuit which is configured to pre-charge a plurality of sense lines to a voltage threshold in a first time period and sense and detect a value of a selected sense line of the sense lines in a second time period.Type: ApplicationFiled: August 23, 2017Publication date: February 28, 2019Inventors: Igor ARSOVSKI, Qing LI, Xiaoli HU, Wei ZHAO, Jieyao LIU
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Patent number: 9570153Abstract: A static random access memory (SRAM) with high efficiency. The SRAM has a first bistable cell, a first bit line, a first complementary bit line, a first word line, and a second word line. The first bistable cell has a first access terminal, a second access terminal, a first access switch and a second access switch. The first access switch is controlled by the first word line to couple the first access terminal to the first bit line. The second access switch is controlled by the second word line to couple the second access terminal to the first complementary bit line.Type: GrantFiled: January 4, 2016Date of Patent: February 14, 2017Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.Inventors: Jiesheng Chen, Jieyao Liu