Abstract: Embodiments of the disclosure include a cache array having a plurality of cache sets grouped into a plurality of subsets. The cache array also includes a read line configured to receive a read signal for the cache array and a set selection line configured to receive a set selection signal. The set selection signal indicates that the read signal corresponds to one of the plurality subsets of the cache array. The read line and the set selection line are operatively coupled to the plurality of cache sets and based on the set selection signal the subset that corresponds to the set selection signal is switched.

Abstract: Embodiments of the disclosure include a cache array having a plurality of cache sets grouped into a plurality of subsets. The cache array also includes a read line configured to receive a read signal for the cache array and a set selection line configured to receive a set selection signal. The set selection signal indicates that the read signal corresponds to one of the plurality subsets of the cache array. The read line and the set selection line are operatively coupled to the plurality of cache sets and based on the set selection signal the subset that corresponds to the set selection signal is switched.

Abstract: Embodiments include a high frequency write through memory device including a plurality of memory cells and a plurality of local evaluation circuits. Each of the plurality of local evaluation circuits are coupled to at least one of the plurality of memory cells and are configured to prevent data stored in the coupled memory cells from being written to a latch node during a write through operation.

Abstract: Embodiments of the disclosure include a cache array having a plurality of cache sets grouped into a plurality of subsets. The cache array also includes a read line configured to receive a read signal for the cache array and a set selection line configured to receive a set selection signal. The set selection signal indicates that the read signal corresponds to one of the plurality subsets of the cache array. The read line and the set selection line are operatively coupled to the plurality of cache sets and based on the set selection signal the subset that corresponds to the set selection signal is switched.

Abstract: A memory apparatus includes a plurality of memory arrays, each memory array including a plurality of memory cells. The apparatus includes a plurality of global bit lines and each one of the global bit lines is connected to a plurality of local bit lines, which are in turn connected to a plurality of memory cells. The apparatus includes a plurality of global bit line (GBL) latches and each GBL latch is located along a separate global bit line to latch a signal along the respective global bit line. The apparatus further includes a plurality of solar bit lines configured to connect the global bit lines to an output latch via a plurality of logic gates.

Abstract: A memory apparatus includes a plurality of memory arrays, each memory array including a plurality of memory cells. The apparatus includes a plurality of global bit lines and each one of the global bit lines is connected to a plurality of local bit lines, which are in turn connected to a plurality of memory cells. The apparatus includes a plurality of global bit line (GBL) latches and each GBL latch is located along a separate global bit line to latch a signal along the respective global bit line. The apparatus further includes a plurality of solar bit lines configured to connect the global bit lines to an output latch via a plurality of logic gates.

Abstract: Embodiments of the disclosure include a high frequency write through memory device including a plurality of memory cells and a plurality of local evaluation circuits. Each of the plurality of local evaluation circuits are coupled to at least one of the plurality of memory cells and are configured to prevent data stored in the coupled memory cells from being written to a latch node during a write through operation.

Abstract: Embodiments of the disclosure include a cache array having a plurality of cache sets grouped into a plurality of subsets. The cache array also includes a read line configured to receive a read signal for the cache array and a set selection line configured to receive a set selection signal. The set selection signal indicates that the read signal corresponds to one of the plurality subsets of the cache array. The read line and the set selection line are operatively coupled to the plurality of cache sets and based on the set selection signal the subset that corresponds to the set selection signal is switched.

Abstract: A method of generating a dynamic port enable signal for gating memory array data to an output node includes generating a programmable leading edge clock signal derivation of an input dynamic clock signal; generating a programmable trailing edge clock signal derivation of the input dynamic clock signal, wherein the leading edge clock signal derivation and the trailing edge clock signal derivation are independently programmable with respect to one another; and gating the generated programmable leading and trailing edge clock signal derivations with a static input enable signal so as to generate the port enable signal such that, when inactive, the port enable signal prevents early memory array data from being coupled to the output node.

Abstract: A jam latch device for a data node includes a feed forward inverter having an input coupled to the data node; a feedback inverter having an input connected to an output of the feed forward inverter with an output of the feedback inverter connected to the data node; an isolation device that selectively decouples the feedback inverter from a power supply rail, the isolation device controlled by a clock signal of a reset device that resets the data node to a first logic state such that decoupling of the feedback inverter from the power supply rail coincides with resetting the data node to the first logic state; and a margin test device that selectively increases pull down strength of the feedback inverter.

Abstract: A method of implementing voltage level shifting for a memory device includes coupling one or more evaluation clock signals to a memory address decode circuit, the one or more evaluation clock signals operating at a first voltage supply level; and coupling a restore clock signal to the memory address decode circuit, the restore clock signal operating at a second voltage supply level that is higher than the first voltage supply level; wherein one or more outputs of the memory address decode circuit operate at the second voltage supply level.

Abstract: An output control circuit for a memory array includes a latched output node precharged to a first logic state prior to both a read and write operation; first logic that couples memory cell data from a memory read path to the output node during the read operation, the first logic controlled by a timing signal; second logic that internally bypasses the memory read path during a write operation by decoupling it from the output node, such that a logical derivative of write data written to the memory array is also coupled to the output node, the second logic also controlled by the timing signal; and wherein a transition of the output node from the first logic state to a second logic state during the write operation occurs within a time range as that of the same transition during the read operation.