Patents by Inventor Jigar Vora

Jigar Vora has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11258671
    Abstract: Systems and methods for functionality management of devices are disclosed. Multiple computing devices may be located in the same environment and/or space and at least two of those computing devices may be configured to perform a given functionality. In these and other examples, one of the devices may be identified as a primary device and the other devices may be identified as secondary devices based on, for example, historical usage data, audio-signal data, computer-vision analysis, and/or one or more other criteria. The functionality may be disabled on the secondary devices until the secondary devices are utilized and/or until a triggering event occurs.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: February 22, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Jigar Vora, Makarand Damle, Aditya Bhave, Ankit Premrajka, Olusanya Temitope Soyannwo
  • Patent number: 10949255
    Abstract: In an embodiment, a processing device receives an instruction to schedule an event associated with a remote target device, generates a schedule for the remote target device, and transmits the schedule to the remote target device. The processing device receives usage information from the remote target device and additional usage information from other remote devices. The processing device applies a machine learning algorithm to the usage information and the additional usage information to determine an update to the schedule. The processing device updates the schedule and sends the update to the remote target device.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: March 16, 2021
    Assignee: Ayla Networks, Inc.
    Inventors: Jigar Vora, Joseph R. Eykholt, Sudha Sundaresan, Pablo Sebastián Rivera, David Russell Friedman, Adrian Caceres
  • Patent number: 10805279
    Abstract: A hardware module for an embedded system comprises a network adapter, a memory and a processing device. The memory stores a shared key and a key identifier (ID) associated with the shared key. The processing device is to connect to a local area network (LAN) using the network adapter. The processing device is further to receive a first notification from a computing device that is also connected to the LAN and determine whether the computing device has access to a copy of the shared key based on the key identifier (ID). Responsive to determining that the computing device has access to the copy of the shared key, the processing device is to use the shared key to generate a session key for a session with the computing device. The processing device may then encrypt communications to the computing device using the session key.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: October 13, 2020
    Assignee: Ayla Networks, Inc.
    Inventors: Jigar Vora, Marko Kiiskila, Daniel Myers, Joseph R. Eykholt, Adrian Caceres
  • Patent number: 10484512
    Abstract: A gateway device includes a first interface to connect to an internet protocol (IP) network and a second interface having a first communication protocol to connect to one or more devices. The gateway device receives an instruction to initiate an attribute update for a device from a remote server via the first interface, the first instruction having a first format. The gateway device determines the attribute update and a virtual device identifier associated with the first device from the first instruction. The gateway device determines the first communication protocol and a first device based at least in part on the first virtual device identifier. The gateway device generates a command for the first device to perform the first attribute update, the command having a second format based at least in part on the first communication protocol, and sends the command to the first device via the second interface.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: November 19, 2019
    Assignee: Ayla Networks, Inc.
    Inventors: Vishwesh Pai, Jigar Vora, Sudha Sundaresan, Daniel Myers, Haoqing Geng
  • Patent number: 10404832
    Abstract: A server determines a plurality of device templates that define a plurality of device attributes of a remote device connected to a gateway device. The server creates a virtual device from the plurality of device templates, wherein the virtual device is a virtual representation of the remote device. The server determines an attribute update for a first device attribute of the remote device. The server updates a second device attribute of the virtual device. The server generates an instruction for the gateway device to initiate the attribute update for the first device attribute. The server transmits the instruction to the gateway device, wherein the instruction causes the gateway device to generate a command for the remote device to perform the attribute update on the device attribute.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: September 3, 2019
    Assignee: Ayla Networks, Inc.
    Inventors: Jigar Vora, Vishwesh Pai, Haoqing Geng, Sudha Sundaresan, Joseph R. Eykholt, Adrian Caceres, Yipei Wang
  • Publication number: 20190155896
    Abstract: In an embodiment, a processing device receives an instruction to schedule an event associated with a remote target device, generates a schedule for the remote target device, and transmits the schedule to the remote target device. The processing device receives usage information from the remote target device and additional usage information from other remote devices. The processing device applies a machine learning algorithm to the usage information and the additional usage information to determine an update to the schedule. The processing device updates the schedule and sends the update to the remote target device.
    Type: Application
    Filed: January 23, 2019
    Publication date: May 23, 2019
    Inventors: Jigar Vora, Joseph R. Eykholt, Sudha Sundaresan, Pablo Sebastián Rivera, David Russell Friedman, Adrian Caceres
  • Patent number: 10223160
    Abstract: A processing device executing a scheduler receives, by a device, a schedule from a remote server computing device, the schedule having a compact format that is understood by the device. The device stores the schedule and the processing device parses the schedule to identify a scheduled event. The processing device executes the scheduled event at a specified time in accordance with the schedule even in the absence of a network connection between the device and the remote server computing device.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: March 5, 2019
    Assignee: Ayla Networks, Inc.
    Inventors: Jigar Vora, Joseph R. Eykholt, Sudha Sundaresan, Pablo Sebastián Rivera, David Russell Friedman, Adrian Caceres
  • Publication number: 20190044926
    Abstract: A hardware module for an embedded system comprises a network adapter, a memory and a processing device. The memory stores a shared key and a key identifier (ID) associated with the shared key. The processing device is to connect to a local area network (LAN) using the network adapter. The processing device is further to receive a first notification from a computing device that is also connected to the LAN and determine whether the computing device has access to a copy of the shared key based on the key identifier (ID). Responsive to determining that the computing device has access to the copy of the shared key, the processing device is to use the shared key to generate a session key for a session with the computing device. The processing device may then encrypt communications to the computing device using the session key.
    Type: Application
    Filed: October 5, 2018
    Publication date: February 7, 2019
    Inventors: Jigar Vora, Marko Kiiskila, Daniel Myers, Joseph R. Eykholt, Adrian Caceres
  • Patent number: 10129226
    Abstract: A hardware module for an embedded system comprises a network adapter, a memory and a processing device. The memory stores a shared key and a key identifier (ID) associated with the shared key. The processing device is to connect to a local area network (LAN) using the network adapter. The processing device is further to receive a first notification from a computing device that is also connected to the LAN and determine whether the computing device has access to a copy of the shared key based on the key identifier (ID). Responsive to determining that the computing device has access to the copy of the shared key, the processing device is to use the shared key to generate a session key for a session with the computing device. The processing device may then encrypt communications to the computing device using the session key.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: November 13, 2018
    Assignee: Ayla Networks, Inc.
    Inventors: Jigar Vora, Marko Kiiskila, Daniel Myers, Joseph R. Eykholt, Adrian Caceres
  • Publication number: 20170064045
    Abstract: A gateway device includes a first interface to connect to an internet protocol (IP) network and a second interface having a first communication protocol to connect to one or more devices. The gateway device receives an instruction to initiate an attribute update for a device from a remote server via the first interface, the first instruction having a first format. The gateway device determines the attribute update and a virtual device identifier associated with the first device from the first instruction. The gateway device determines the first communication protocol and a first device based at least in part on the first virtual device identifier. The gateway device generates a command for the first device to perform the first attribute update, the command having a second format based at least in part on the first communication protocol, and sends the command to the first device via the second interface.
    Type: Application
    Filed: August 30, 2016
    Publication date: March 2, 2017
    Inventors: Vishwesh Pai, Jigar Vora, Sudha Sundaresan, Daniel Myers, Haoqing Geng
  • Publication number: 20170064042
    Abstract: A server determines a plurality of device templates that define a plurality of device attributes of a remote device connected to a gateway device. The server creates a virtual device from the plurality of device templates, wherein the virtual device is a virtual representation of the remote device. The server determines an attribute update for a first device attribute of the remote device. The server updates a second device attribute of the virtual device. The server generates an instruction for the gateway device to initiate the attribute update for the first device attribute. The server transmits the instruction to the gateway device, wherein the instruction causes the gateway device to generate a command for the remote device to perform the attribute update on the device attribute.
    Type: Application
    Filed: August 29, 2016
    Publication date: March 2, 2017
    Inventors: Jigar Vora, Vishwesh Pai, Haoqing Geng, Sudha Sundaresan, Joseph R. Eykholt, Adrian Caceres, Yipei Wang
  • Publication number: 20170060629
    Abstract: A processing device executing a scheduler receives, by a device, a schedule from a remote server computing device, the schedule having a compact format that is understood by the device. The device stores the schedule and the processing device parses the schedule to identify a scheduled event. The processing device executes the scheduled event at a specified time in accordance with the schedule even in the absence of a network connection between the device and the remote server computing device.
    Type: Application
    Filed: August 29, 2016
    Publication date: March 2, 2017
    Inventors: Jigar Vora, Joseph R. Eykholt, Sudha Sundaresan, Pablo Sebastián Rivera, David Russell Friedman, Adrian Caceres
  • Publication number: 20160352701
    Abstract: A hardware module for an embedded system comprises a network adapter, a memory and a processing device. The memory stores a shared key and a key identifier (ID) associated with the shared key. The processing device is to connect to a local area network (LAN) using the network adapter. The processing device is further to receive a first notification from a computing device that is also connected to the LAN and determine whether the computing device has access to a copy of the shared key based on the key identifier (ID). Responsive to determining that the computing device has access to the copy of the shared key, the processing device is to use the shared key to generate a session key for a session with the computing device. The processing device may then encrypt communications to the computing device using the session key.
    Type: Application
    Filed: August 10, 2016
    Publication date: December 1, 2016
    Inventors: Jigar Vora, Marko Kiiskila, Daniel Myers, Joseph R. Eykholt, Adrian Caceres
  • Patent number: 9426185
    Abstract: A computing device connects to a local area network (LAN) and determines whether a device comprising an embedded system is also connected to the LAN. Responsive to determining that the device is connected to the LAN, the computing device establishes a first session with the embedded system of the device over the LAN and then communicates with the embedded system of the device via the first session.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: August 23, 2016
    Assignee: Ayla Networks, Inc.
    Inventors: Jigar Vora, Marko Kiiskila, Daniel Myers, Joseph R. Eykholt, Adrian Caceres
  • Publication number: 20110317496
    Abstract: A jam latch device for a data node includes a feed forward inverter having an input coupled to the data node; a feedback inverter having an input connected to an output of the feed forward inverter with an output of the feedback inverter connected to the data node; an isolation device that selectively decouples the feedback inverter from a power supply rail, the isolation device controlled by a clock signal of a reset device that resets the data node to a first logic state such that decoupling of the feedback inverter from the power supply rail coincides with resetting the data node to the first logic state; and a margin test device that selectively increases pull down strength of the feedback inverter.
    Type: Application
    Filed: June 23, 2010
    Publication date: December 29, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul A. Bunce, John D. Davis, Diana M. Henderson, Jigar Vora
  • Publication number: 20110320851
    Abstract: A method of generating a dynamic port enable signal for gating memory array data to an output node includes generating a programmable leading edge clock signal derivation of an input dynamic clock signal; generating a programmable trailing edge clock signal derivation of the input dynamic clock signal, wherein the leading edge clock signal derivation and the trailing edge clock signal derivation are independently programmable with respect to one another; and gating the generated programmable leading and trailing edge clock signal derivations with a static input enable signal so as to generate the port enable signal such that, when inactive, the port enable signal prevents early memory array data from being coupled to the output node.
    Type: Application
    Filed: June 23, 2010
    Publication date: December 29, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul A. Bunce, John D. Davis, Diana M. Henderson, Jigar Vora
  • Publication number: 20110317505
    Abstract: An output control circuit for a memory array includes a latched output node precharged to a first logic state prior to both a read and write operation; first logic that couples memory cell data from a memory read path to the output node during the read operation, the first logic controlled by a timing signal; second logic that internally bypasses the memory read path during a write operation by decoupling it from the output node, such that a logical derivative of write data written to the memory array is also coupled to the output node, the second logic also controlled by the timing signal; and wherein a transition of the output node from the first logic state to a second logic state during the write operation occurs within a time range as that of the same transition during the read operation.
    Type: Application
    Filed: June 23, 2010
    Publication date: December 29, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul A. Bunce, John D. Davis, Diana M. Henderson, Jigar Vora
  • Publication number: 20110317499
    Abstract: A method of implementing voltage level shifting for a memory device includes coupling one or more evaluation clock signals to a memory address decode circuit, the one or more evaluation clock signals operating at a first voltage supply level; and coupling a restore clock signal to the memory address decode circuit, the restore clock signal operating at a second voltage supply level that is higher than the first voltage supply level; wherein one or more outputs of the memory address decode circuit operate at the second voltage supply level.
    Type: Application
    Filed: June 23, 2010
    Publication date: December 29, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul A. Bunce, John D. Davis, Diana M. Henderson, Jigar Vora