Patents by Inventor Jigish D. Trivedi
Jigish D. Trivedi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8971086Abstract: A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer.Type: GrantFiled: June 14, 2013Date of Patent: March 3, 2015Assignee: Micron Technology, Inc.Inventors: Suraj Mathew, Jigish D. Trivedi
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Publication number: 20130279277Abstract: A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer.Type: ApplicationFiled: June 14, 2013Publication date: October 24, 2013Inventors: Suraj Mathew, Jigish D. Trivedi
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Patent number: 8541836Abstract: Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.Type: GrantFiled: November 12, 2012Date of Patent: September 24, 2013Assignee: Micron Technology, Inc.Inventors: Kurt D. Beigel, Jigish D. Trivedi, Kevin G. Duesman
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Patent number: 8466517Abstract: A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer.Type: GrantFiled: April 12, 2012Date of Patent: June 18, 2013Assignee: Micron Technology, Inc.Inventors: Suraj Mathew, Jigish D. Trivedi
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Patent number: 8319280Abstract: Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.Type: GrantFiled: September 13, 2011Date of Patent: November 27, 2012Assignee: Micron Technology, Inc.Inventors: Kurt D. Beigel, Jigish D. Trivedi, Kevin G. Duesman
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Publication number: 20120199908Abstract: A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer.Type: ApplicationFiled: April 12, 2012Publication date: August 9, 2012Applicant: Micron Technology, Inc.Inventors: Suraj Mathew, Jigish D. Trivedi
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Patent number: 8158471Abstract: A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer.Type: GrantFiled: October 5, 2010Date of Patent: April 17, 2012Assignee: Micron Technology, Inc.Inventors: Suraj Mathew, Jigish D Trivedi
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Publication number: 20120001245Abstract: Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.Type: ApplicationFiled: September 13, 2011Publication date: January 5, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Kurt D. Beigel, Jigish D. Trivedi, Kevin G. Duesman
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Patent number: 8067286Abstract: The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access device trenches, and source/drain regions are formed proximate the electrically conductive material. The electrically conductive material and source/drain regions together are incorporated into a pair of adjacent recessed access devices. After the recessed access device trenches are formed within the substrate, an isolation region trench is formed between the adjacent recessed access devices and filled with electrically insulative material to form a trenched isolation region.Type: GrantFiled: January 24, 2011Date of Patent: November 29, 2011Assignee: Micron Technology, Inc.Inventors: Kunal R. Parekh, Suraj J. Mathew, Jigish D. Trivedi, John K. Zahurak, Sanh D. Tang
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Patent number: 8035160Abstract: Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.Type: GrantFiled: November 30, 2009Date of Patent: October 11, 2011Assignee: Micron Technology, Inc.Inventors: Kurt D. Beigel, Jigish D. Trivedi, Kevin G. Duesman
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Patent number: 8003526Abstract: A process for forming a local interconnect includes applying a layer of metal over a semiconductor layer. A layer of metal silicide is formed over the layer of metal. The layer of metal silicide is patterned to define the boundaries of the local interconnect. The metal silicide is reacted with the layer of metal to form a composite structure. The composite structure includes the metal silicide, another metal silicide formed as silicon from the metal silicide reacts with the underlying layer of metal and an intermetallic compound of the metal from the layer of metal and metal from the layer of metal silicide. The unreacted layer of metal is removed with the composite structure remaining as the local interconnect.Type: GrantFiled: March 10, 2010Date of Patent: August 23, 2011Assignee: Micron Technology, Inc.Inventor: Jigish D. Trivedi
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Publication number: 20110117725Abstract: The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access device trenches, and source/drain regions are formed proximate the electrically conductive material. The electrically conductive material and source/drain regions together are incorporated into a pair of adjacent recessed access devices. After the recessed access device trenches are formed within the substrate, an isolation region trench is formed between the adjacent recessed access devices and filled with electrically insulative material to form a trenched isolation region.Type: ApplicationFiled: January 24, 2011Publication date: May 19, 2011Applicant: Micron Technology, Inc.Inventors: Kunal R. Parekh, Suraj Mathew, Jigish D. Trivedi, John K. Zahurak, Sanh D. Tang
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Patent number: 7919829Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content near the trench walls to protect the walls. The silicon nitride layer further from the trench walls has a low nitrogen content and a high silicon content, to allow improved adhesion. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator. The resulting trench has a well-adhered insulator which helps the insulating properties of the trench.Type: GrantFiled: August 28, 2007Date of Patent: April 5, 2011Assignee: Micron Technology, Inc.Inventors: Jigish D. Trivedi, Robert D. Patraw, Kevin L. Beaman, John A. Smythe, III
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Patent number: 7897460Abstract: The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access device trenches, and source/drain regions are formed proximate the electrically conductive material. The electrically conductive material and source/drain regions together are incorporated into a pair of adjacent recessed access devices. After the recessed access device trenches are formed within the substrate, an isolation region trench is formed between the adjacent recessed access devices and filled with electrically insulative material to form a trenched isolation region.Type: GrantFiled: March 19, 2008Date of Patent: March 1, 2011Assignee: Micron Technology, Inc.Inventors: Kunal R. Parekh, Suraj Mathew, Jigish D. Trivedi, John K. Zahurak, Sanh D. Tang
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Publication number: 20110020988Abstract: A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer.Type: ApplicationFiled: October 5, 2010Publication date: January 27, 2011Applicant: Micron Technology, Inc.Inventors: SURAJ MATHEW, Jigish D. Trivedi
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Patent number: 7829399Abstract: A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer.Type: GrantFiled: April 10, 2009Date of Patent: November 9, 2010Assignee: Micron Technology, Inc.Inventors: Suraj Mathew, Jigish D Trivedi
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Publication number: 20100167528Abstract: A process for forming a local interconnect includes applying a layer of metal over a semiconductor layer. A layer of metal silicide is formed over the layer of metal. The layer of metal silicide is patterned to define the boundaries of the local interconnect. The metal silicide is reacted with the layer of metal to form a composite structure. The composite structure includes the metal silicide, another metal silicide formed as silicon from the metal silicide reacts with the underlying layer of metal and an intermetallic compound of the metal from the layer of metal and metal from the layer of metal silicide. The unreacted layer of metal is removed with the composite structure remaining as the local interconnect.Type: ApplicationFiled: March 10, 2010Publication date: July 1, 2010Inventor: Jigish D. Trivedi
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Patent number: 7701059Abstract: A process for forming a local interconnect includes applying a layer of metal over a semiconductor layer. A layer of metal silicide is formed over the layer of metal. The layer of metal silicide is patterned to define the boundaries of the local interconnect. The metal silicide is reacted with the layer of metal to form a composite structure. The composite structure includes the metal silicide, another metal silicide formed as silicon from the metal silicide reacts with the underlying layer of metal and an intermetallic compound of the metal from the layer of metal and metal from the layer of metal silicide. The unreacted layer of metal is removed with the composite structure remaining as the local interconnect.Type: GrantFiled: August 21, 1997Date of Patent: April 20, 2010Assignee: Micron Technology, Inc.Inventor: Jigish D. Trivedi
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Publication number: 20100072532Abstract: Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.Type: ApplicationFiled: November 30, 2009Publication date: March 25, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Kurt D. Beigel, Jigish D. Trivedi, Kevin G. Duesman
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Patent number: 7659181Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the trench. An expandable, oxidizable liner, preferably amorphous silicon, is then deposited. The trench is then filled with a spin-on dielectric (SOD) material. A densification process is then applied, whereby the SOD material contracts and the oxidizable liner expands. Preferably, the temperature is ramped up while oxidizing during at least part of the densification process. The resulting trench has a negligible vertical wet etch rate gradient and a negligible recess at the top of the trench.Type: GrantFiled: November 6, 2006Date of Patent: February 9, 2010Assignee: Micron Technology, Inc.Inventors: John A. Smythe, III, Jigish D. Trivedi