Abstract: A high electron mobility transistor device including a channel layer, a first barrier layer, and a P-type gallium nitride layer is provided. The first barrier layer is disposed on the channel layer. The P-type gallium nitride layer is disposed on the first barrier layer. The first thickness of the first barrier layer located directly under the P-type gallium nitride layer is greater than the second thickness of the first barrier layer located on two sides of the P-type gallium nitride layer.

Abstract: A suction device and a suction force adjustment method thereof are provided. A detecting device collects sound generated when the suction device executes a suction operation to obtain characteristics of a sound signal. The detecting device determines a clogging degree of a filter disposed on an exhaust vent of a suction unit, an airflow velocity in a suction pipe, a material of the suctioned surface, and a degree of closure between a suction port of the suction device and the suctioned surface according to the characteristics of the sound signal. A control host adjusts a suction force of the suction unit or adjusts the degree of closure between the suction port of the suction device and the suctioned surface according to a detected result of the detecting device, and provides warning information for cleaning or replacing the filter.

Abstract: A flossing tool comprises in general a fork shape handle body, a lever and a rotor. The handle body has eyelets to direct the floss. The lever is pivoted on the neck of the handle body to stretch the floss directly or via the rotor. The rotor has one or two reels for winding the floss. The tool provides constant controllable tensioning and easy advancing operation of the floss. Four embodiments are illustrated in this invention, in the fourth embodiment a floss container is included.

Abstract: A fan capable of resisting reversed flow includes a frame body, a fan wheel and at least two baffle parts. The frame body has an inlet and an outlet and provides at least an actuating device at the outlet side. The fan wheel is rotationally attached to the inner side of the frame body and provides a hub and a plurality of fan blades extending outward radially along the periphery of the hub. One of the baffle parts is pivotally connected to the outlet side of the frame body and the first baffle part connecting with the actuating device. When the fan stops running, the other baffle part, which is without connecting with the actuating device, pushes the slide element of the actuating device to slide for the baffle part closing the outlet.

Abstract: A split gate flash memory cell. The memory cell includes a substrate, a conductive line, source/drain regions, an insulating layer, a conductive spacer, an insulating stud, a first conductive layer, and a first insulating spacer. The conductive line is disposed in a lower portion of the trench of the substrate. The source region is formed in the substrate adjacent to an upper portion of the conductive line having the insulating layer thereon. The conductive spacer is disposed on the upper sidewall of the trench serving as a floating gate. The insulating stud is disposed on the insulating layer. The first conductive layer is disposed over the substrate adjacent to the conductive spacer serving as a control gate. The first insulating spacer is disposed on the sidewall of the insulating stud to cover the first conductive layer. The drain region is formed in the substrate adjacent to the first conductive layer.

Abstract: A split gate flash memory cell. The memory cell includes a substrate, a conductive line, source/drain regions, an insulating layer, a conductive spacer, an insulating stud, a first conductive layer, and a first insulating spacer. The conductive line is disposed in a lower portion of the trench of the substrate. The source region is formed in the substrate adjacent to an upper portion of the conductive line having the insulating layer thereon. The conductive spacer is disposed on the upper sidewall of the trench serving as a floating gate. The insulating stud is disposed on the insulating layer. The first conductive layer is disposed over the substrate adjacent to the conductive spacer serving as a control gate. The first insulating spacer is disposed on the sidewall of the insulating stud to cover the first conductive layer. The drain region is formed in the substrate adjacent to the first conductive layer.

Abstract: A split gate flash memory cell. The memory cell includes a substrate, a conductive stud, source/drain regions, an insulating layer, a conductive spacer, an insulating stud, a first conductive layer, and a first insulating spacer. The conductive stud is disposed in the lower trench of the substrate. The source region is formed in the substrate adjacent to the upper conductive stud having the insulating layer thereon. The conductive spacer is disposed on the upper sidewall of the trench serving as a floating gate. The insulating stud is disposed on the insulating layer. The first conductive layer is disposed over the substrate of the outside conductive spacer serving as a control gate. The first insulating spacer is disposed on the sidewall of the insulating stud to cover the first conductive layer. The drain region is formed in the substrate of the outside first conductive layer.

Abstract: A split gate flash memory cell. The memory cell includes a substrate, a conductive stud, source/drain regions, an insulating layer, a conductive spacer, an insulating stud, a first conductive layer, and a first insulating spacer. The conductive stud is disposed in the lower trench of the substrate. The source region is formed in the substrate adjacent to the upper conductive stud having the insulating layer thereon. The conductive spacer is disposed on the upper sidewall of the trench serving as a floating gate. The insulating stud is disposed on the insulating layer. The first conductive layer is disposed over the substrate of the outside conductive spacer serving as a control gate. The first insulating spacer is disposed on the sidewall of the insulating stud to cover the first conductive layer. The drain region is formed in the substrate of the outside first conductive layer.

Abstract: The present invention provides a multiple exposure method for defining a rectangular pattern on a photoresist layer. The method comprises the following steps. First, a rectangular region is defined on the photoresist layer, having a first margin pair and a second margin pair corresponding to the rectangular pattern. Next, a first exposure process is performed on a first exposure region of the photoresist layer. An extension of the first margin pair acts as a boundary between the first exposure region and the rectangular region. Next, a second exposure process is performed on a second exposure region of the photoresist layer. An extension of the second margin pair acts as a boundary between the second exposure region and the rectangular region. Finally, a development process is performed on the first exposure region and the second exposure region to create the rectangular pattern on a substrate.

Abstract: The present invention provides a multiple exposure method for defining a rectangular pattern on a photoresist layer. The method comprises the following steps. First, a rectangular region is defined on the photoresist layer, having a first margin pair and a second margin pair corresponding to the rectangular pattern. Next, a first exposure process is performed on a first exposure region of the photoresist layer. An extension of the first margin pair acts as a boundary between the first exposure region and the rectangular region. Next, a second exposure process is performed on a second exposure region of the photoresist layer. An extension of the second margin pair acts as a boundary between the second exposure region and the rectangular region. Finally, a development process is performed on the first exposure region and the second exposure region to create the rectangular pattern on a substrate.

Abstract: A structure of building-block type members for assembly of computer components permitting spatial variation, within, blocks in pillar and tube of same length and equally spaced are butted to a monitor and the main unit with the circumference of the tube in diameter not greater than the spacing between any two abutted pillars of surrounding four pillars; said tubes are provided on the back panel of the monitor, and pillars, on the sides of the main unit combine the monitor and main unit allowing optimal space use for combination as desired and the additional of peripherals.

Abstract: A method for manufacturing a capacitor includes the steps of a) forming a first sacrificial layer over the etching stop layer; b) partially removing the first sacrificial layer, the etching stop layer, and the dielectric layer to form a contact window, c) forming a first conducting layer over the first sacrificial layer and in the contact window, d) forming a second sacrificial layer over the first conducting layer, e) partially removing the second sacrificial layer, the first conducting layer, and the first sacrificial layer to expose a portion of the first sacrificial layer, f) forming a second conducting layer alongside the second sacrificial layer, the first conducting layer, and the portion of the first sacrificial layer, and g) removing the first and second sacrificial layers to expose the etching stop layer, wherein the remained first conducting layer and the second conducting layer construct a capacitor plate with a generally crosssectionally modified H-shaped structure.

Abstract: A method for manufacturing a capacitor, applied to a memory unit including a substrate forming thereon a dielectric layer forming thereon a first conducting layer, includes the steps of a) forming a sacrificial layer over the first conducting layer, b) partially removing the sacrificial layer, the first conducting layer, and the dielectric layer to form a contact window, c) forming a second conducting layer over the sacrificial layer and in the contact window, d) partially removing the second conducting layer and the sacrificial layer to expose a portion of the sacrificial layer and retain a portion of the second conducting layer, and e) forming a third conducting layer alongside the portions of the second conducting layer and the sacrificial layer, and removing the portion of the sacrificial layer to expose the first conducting layer, wherein the first conducting layer, the portion of the second conducting layer, and the third conducting layer construct a capacitor plate with a generally crosssectionally mod

Abstract: A method for manufacturing a capacitor, applied to a memory unit including a substrate forming thereon a dielectric layer forming thereon a first conducting layer, includes the steps of a) forming a first sacrificial layer over the first conducting layer, b) partially removing the first sacrificial layer, the first conducting layer, and the dielectric layer to form a contact window, c) forming a second conducting layer over the first sacrificial layer and in the contact window, d) forming a second sacrificial layer over the second conducting layer, e) partially removing the second sacrificial layer, the second conducting layer, and the first sacrificial layer to expose a portion of the first sacrificial layer, f) forming a third conducting layer alongside the second sacrificial layer, the second conducting layer, and the portion of the first sacrificial layer, g) removing the first and second sacrificial layers to expose the first conducting layer, and h) partially removing the first conducting layer while re

Abstract: A memory device, such as a flash EEPROM, has zero birds' beaks and vertically overlapping gates to facilitate high cell density in the EEPROM's core. During fabrication, a layer of field oxide is formed over the core. The active regions are exposed by etching through the layer of field oxide to form vertically walled cavities around the active regions. The tunnel oxide, floating gate, interpoly dielectric, and the control gate are formed within each cavity so that the floating gate overlaps the control gate along the vertical walls. As a result, capacitive coupling between the gates is maintained, yet the horizontal dimensions of the cell decrease. Similarly, the absence of birds' beaks facilitates higher cell density in the core.

Abstract: A memory device, such as a flash EEPROM, has zero birds' beaks and vertically overlapping gates to facilitate high cell density in the EEPROM's core. During fabrication, a layer of field oxide is formed over the core. The active regions are exposed by etching through the layer of field oxide to form vertically walled cavities around the active regions. The tunnel oxide, floating gate, interpoly dielectric, and the control gate are formed within each cavity so that the floating gate overlaps the control gate along the vertical walls. As a result, capacitive coupling between the gates is maintained, yet the horizontal dimensions of the cell decrease. Similarly, the absence of birds' beaks facilitates higher cell density in the core.

Abstract: A process of forming field oxide regions using a field oxidation performed in a dry oxidation environment in a temperature equal to or greater than approximately 1000.degree. C. The dry oxidation reduces or eliminates the formation of Kooi ribbons, and the high temperature field oxidation allows the field oxide to flow, thereby reducing physical stresses normally associated with field oxidation performed at temperatures below 1000.degree. C. The high temperature field oxidation also greatly reduces the ratio of the length of the bird's beaks formed during the field oxidation to the thickness of the field oxide, allowing smaller active regions to be formed. The thinner field oxide regions, in turn, make it possible to perform the field implant after the field oxidation, thereby avoiding the lateral encroachment problem and controlling source to drain or drain to source punch-through under the gate.