Abstract: A semiconductor structure is provided. The semiconductor structure includes at least one metal gate structure and a device to be tested. The metal gate structure is disposed on a substrate. The device to be tested is disposed on the metal gate structure and electrically separated from the metal gate structure. The device to be tested is heated by a heat generated when the metal gate structure is applied with a voltage.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate having at least a gate structure formed thereon, forming LDDs in the substrate respectively at two side of the gate structure and a spacer at sidewalls of the gate structure, forming a source/drain in the substrate at two side of the gate structure, performing ant etching process to form recesses respectively in the source/drain, forming a barrier layer in the recesses; and performing a salicide process.

Abstract: A method for forming a SiGe epitaxial layer is described. A first SEG process is performed under a first condition, consuming about 1% to 20% of the total process time for forming the SiGe epitaxial layer. Then, a second SEG process is performed under a second condition, consuming about 99% to 80% of the total process time. The first condition and the second condition include different temperatures or pressures. The first and the second SEG processes each uses a reactant gas that includes at least a Si-containing gas and a Ge-containing gas.

Abstract: A method of manufacturing a metal-oxide-semiconductor transistor device is disclosed, in which, an insulation region is formed to define the insulation region and an active region, wherein the active region is adjacent to the insulation region and electrically insulated by the insulation region. A selective epitaxial process is performed to form an epitaxial layer on the active region; wherein the epitaxial layer laterally extends onto a surface of a peripheral portion of the insulation region. Thereafter, a doped well is formed in the semiconductor substrate of the active region. A gate structure is formed on the epitaxial layer. Finally, a drain/source region is formed in the semiconductor substrate and the epitaxial layer at a side of the gate structure.

Abstract: A complementary metal-oxide-semiconductor (CMOS) device includes a substrate with a first active region and a second active region; a first gate structure and a second gate structure, respectively disposed on the first active region and the second active region; a first spacer structure and a second spacer structure respectively disposed on sidewalls of the first gate structure and the second gate structure; a first LDD and a second LDD respectively disposed in the substrate at both sides of the first gate structure and the second gate structure; an epitaxial material layer, disposed in the first active region and located on a side of the first LDD; and a passivation layer, disposed on the first gate structure, the first spacer structure, and the first LDD and covering the second active region, wherein the passivation layer comprises a carbon-containing oxynitride layer.

Abstract: A complementary metal-oxide-semiconductor (CMOS) device includes a substrate with a first active region and a second active region; a first gate structure and a second gate structure, respectively disposed on the first active region and the second active region; a first spacer structure and a second spacer structure respectively disposed on sidewalls of the first gate structure and the second gate structure; a first LDD and a second LDD respectively disposed in the substrate at both sides of the first gate structure and the second gate structure; an epitaxial material layer, disposed in the first active region and located on a side of the first LDD; and a passivation layer, disposed on the first gate structure, the first spacer structure, and the first LDD and covering the second active region, wherein the passivation layer comprises a carbon-containing oxynitride layer.

Abstract: A method for forming a SiGe epitaxial layer is described. A first SEG process is performed under a first condition, consuming about 1% to 20% of the total process time for forming the SiGe epitaxial layer. Then, a second SEG process is performed under a second condition, consuming about 99% to 80% of the total process time. The first condition and the second condition include different temperatures or pressures. The first and the second SEG processes each uses a reactant gas that includes at least a Si-containing gas and a Ge-containing gas.

Abstract: A complementary metal-oxide-semiconductor (CMOS) device includes a substrate with a first active region and a second active region; a first gate structure and a second gate structure, respectively disposed on the first active region and the second active region; a first spacer structure and a second spacer structure respectively disposed on sidewalls of the first gate structure and the second gate structure; a first LDD and a second LDD respectively disposed in the substrate at both sides of the first gate structure and the second gate structure; an epitaxial material layer, disposed in the first active region and located on a side of the first LDD; and a passivation layer, disposed on the first gate structure, the first spacer structure, and the first LDD and covering the second active region, wherein the passivation layer comprises a carbon-containing oxynitride layer.

Abstract: A metal-oxide-semiconductor transistor device comprises a semiconductor substrate comprising an active region and an insulation region, a selective epitaxial layer between the active region and a gate structure, wherein a peripheral portion of the epitaxial layer is over a peripheral portion of the insulation region, such that the width of the channel is increased and a drain current is improved.

Abstract: Method of making an electroplated interconnection wire of a composite of metal and carbon nanotubes is disclosed, including electroplating a substrate having a conductive baseline on a surface thereof in an electroplating bath containing a metal ion and carbon nanotubes, so that an electroplated interconnection wire of a composite of the metal and carbon nanotubes is formed on the conductive baseline. Alternatively, a method of the present invention includes preparing a dispersion of carbon nanotubes dispersed in an organic solvent, printing a baseline with the dispersion on a surface of a substrate, evaporating the organic solvent to obtain a conductive baseline, and electroplating the surface in an electroplating bath containing a metal ion, so that an electroplated interconnection wire of a composite of the metal and carbon nanotubes is formed on the conductive baseline.

Abstract: Method of making an electroplated interconnection wire of a composite of metal and carbon nanotubes is disclosed, including electroplating a substrate having a conductive baseline on a surface thereof in an electroplating bath containing a metal ion and carbon nanotubes, so that an electroplated interconnection wire of a composite of the metal and carbon nanotubes is formed on the conductive baseline. Alternatively, a method of the present invention includes preparing a dispersion of carbon nanotubes dispersed in an organic solvent, printing a baseline with the dispersion on a surface of a substrate, evaporating the organic solvent to obtain a conductive baseline, and electroplating the surface in an electroplating bath containing a metal ion, so that an electroplated interconnection wire of a composite of the metal and carbon nanotubes is formed on the conductive baseline.

Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate, a gate structure, a spacer, a SixGey layer and a SixGey protection layer. The gate structure is deposited on the substrate and the spacer is deposited on the sidewalls of the gate structure. The SixGey layer is deposited in the substrate on both sides of the spacer and extended to a portion beneath part of the spacer. In addition, the top level of the SixGey layer is higher than the surface of the substrate. Moreover, the SixGey protection layer is deposited on the SixGey layer and the SixGey protection layer comprises Six1Gey1, where 0?y1<y.

Abstract: Carbon nanotubes are directly grown on a substrate surface having three metal layers thereon by a thermal chemical vapor deposition at low-temperature, which can be used as an electron emission source for field emission displays. The three layers include a layer of an active metal catalyst sandwiched between a thick metal support layer formed on the substrate and a bonding metal layer. The active metal catalyst is iron, cobalt, nickel or an alloy thereof; the metal support and the bonding metal independently are Au, Ag, Cu, Pd, Pt or an alloy thereof; and they can be formed by sputtering, chemical vapor deposition, physical vapor deposition, screen printing or electroplating.

Abstract: A manufacturing method of carbon nanotube transistors is disclosed. The steps include: forming an insulating layer on a substrate; forming a first oxide layer on the insulating layer using a solution with cobalt ion catalyst by spin-on-glass (SOG); forming a second oxide layer on the first oxide layer using a solution without the catalyst; forming a blind hole on the second oxide layer using photolithographic and etching processes, the blind hole exposing the first oxide layer, the sidewall of the second oxide layer, and the insulating layer; forming a single wall carbon nanotube (SWNT) connecting the first oxide layer separated by the blind hole and parallel to the substrate; and forming a source and a drain connecting to both ends of the SWNT, respectively.

Abstract: The present invention discloses a supported metal catalyst useful in synthesizing carbon nanotubes by low-temperature (<600° C.) thermal chemical vapor deposition (CVD), which contains particles of a noble metal having a diameter of 0.1-10 microns as a support and a metal catalyst deposited on the support. The metal catalyst is iron, cobalt, nickel or an alloy thereof. The weight ratio of the metal catalyst to the support ranges from 0.1:100 to 10:100. The present invention also discloses a method of synthesizing carbon nanotubes directly on a substrate by low-temperature thermal CVD, wherein the support is not needed to be removed from the substrate after growth of carbon nanotubes.

Abstract: Carbon nanotubes are directly grown on a substrate surface having three metal layers thereon by a thermal chemical vapor deposition at low-temperature, which can be used as an electron emission source for field emission displays. The three layers include a layer of an active metal catalyst sandwiched between a thick metal support layer formed on the substrate and a bonding metal layer. The active metal catalyst is iron, cobalt, nickel or an alloy thereof; the metal support and the bonding metal independently are Au, Ag, Cu, Pd, Pt or an alloy thereof; and they can be formed by sputtering, chemical vapor deposition, physical vapor deposition, screen printing or electroplating.

Abstract: A combinative carbon material is presented. A large-sized carbon material serving as a support combines with a nano-sized fibrous carbon material, which grows on the support. In addition to the support, a catalyst system includes an active nanocatalyst and an optional co-catalyst. The catalyst system is then reacted with a carbon source at an elevated temperature to form a combinative carbon material.