Patents by Inventor Jihong Chen
Jihong Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090220788Abstract: Adsorbed gaseous species and elements in a carbon (C) powder and a graphite crucible are reduced by way of a vacuum and an elevated temperature sufficient to cause reduction. A wall and at least one end of an interior of the crucible is lined with C powder purified in the above manner. An Si+C mixture is formed with C powder purified in the above manner and Si powder or granules. The lined crucible is charged with the Si+C mixture. Adsorbed gaseous species and elements are reduced from the Si+C mixture and the crucible by way of a vacuum and an elevated temperature that is sufficient to cause reduction but which does not exceed the melting point of Si. Thereafter, by way of a vacuum and an elevated temperature, the Si+C mixture is caused to react and form polycrystalline SiC.Type: ApplicationFiled: December 7, 2006Publication date: September 3, 2009Applicant: II-VI INCORPORATEDInventors: Donovan L. Barrett, Jihong Chen, Richard H. Hopkins, Carl J. Johnson
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Publication number: 20090181506Abstract: An embedded memory device and method of forming MOS transistors having reduced masking requirements and defects using a single drain sided halo implant in the NMOS FLASH or EEPROM memory regions is discussed. The memory device comprises a memory region and a logic region. Logic transistors within the logic region have halos implanted at an angle underlying the channel from both drain and source region sides. Asymmetric memory cell transistors within the memory region receive a selective halo implant only from the drain side of the channel and not from the source side to form a larger halo on the drain side and leave a higher dopant concentration more deeply into the source side.Type: ApplicationFiled: March 19, 2009Publication date: July 16, 2009Applicant: Texas Instruments IncorporatedInventors: Jihong Chen, Eddie Hearl Breashears, Xin Wang, John Howard Macpeak
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Publication number: 20080190355Abstract: The invention relates to substrates of semi-insulating silicon carbide used for semiconductor devices and a method for making the same. The substrates have a resistivity above 106 Ohm-cm, and preferably above 108 Ohm-cm, and most preferably above 109 Ohm-cm, and a capacitance below 5 pF/mm2 and preferably below 1 pF/mm2. The electrical properties of the substrates are controlled by a small amount of added deep level impurity, large enough in concentration to dominate the electrical behavior, but small enough to avoid structural defects. The substrates have concentrations of unintentional background impurities, including shallow donors and acceptors, purposely reduced to below 5·1016 cm?3, and preferably to below 1·1016 cm?3, and the concentration of deep level impurity is higher, and preferably at least two times higher, than the difference between the concentrations of shallow acceptors and shallow donors.Type: ApplicationFiled: July 6, 2005Publication date: August 14, 2008Applicant: II-VI INCORPORATEDInventors: Jihong Chen, Ilya Zwieback, Avinash K. Gupta, Donovan L. Barrett, Richard H. Hopkins, Edward Semenas, Thomas A. Anderson, Andrew E. Souzis
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Patent number: 7371648Abstract: The present invention provides a method for manufacturing a transistor device, and a method for manufacturing an integrated circuit including the same. The method for manufacturing the transistor device, among other elements, includes forming a gate structure over a substrate, implanting an atom selected from the group consisting of fluorine, silicon, or germanium into the substrate proximate the gate structure to cause at least a portion of the substrate to be in a sub-amorphous state, and implanting a dopant into the substrate having the implanted atom therein, thereby forming source/drain regions in the substrate, wherein the transistor device does not have a halo/pocket implant.Type: GrantFiled: September 1, 2006Date of Patent: May 13, 2008Assignee: Texas Instruments IncorporatedInventors: Jihong Chen, Srinivasan Chakravarthi, Eddie H. Breashears, Amitabh Jain
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Publication number: 20080057654Abstract: The present invention provides a method for manufacturing a transistor device, and a method for manufacturing an integrated circuit including the same. The method for manufacturing the transistor device, among other elements, includes forming a gate structure over a substrate, implanting an atom selected from the group consisting of fluorine, silicon, or germanium into the substrate proximate the gate structure to cause at least a portion of the substrate to be in a sub-amorphous state, and implanting a dopant into the substrate having the implanted atom therein, thereby forming source/drain regions in the substrate, wherein the transistor device does not have a halo/pocket implant.Type: ApplicationFiled: September 1, 2006Publication date: March 6, 2008Applicant: Texas Instruments, IncorporatedInventors: Jihong Chen, Srinivasan Chakravarthi, Eddie H. Breashears, Amitabh Jain
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Publication number: 20070278557Abstract: An embedded memory device and method of forming MOS transistors having reduced masking requirements and defects using a single drain sided halo implant in the NMOS FLASH or EEPROM memory regions is discussed. The memory device comprises a memory region and a logic region. Logic transistors within the logic region have halos implanted at an angle underlying the channel from both drain and source region sides. Asymmetric memory cell transistors within the memory region receive a selective halo implant only from the drain side of the channel and not from the source side to form a larger halo on the drain side and leave a higher dopant concentration more deeply into the source side.Type: ApplicationFiled: May 31, 2006Publication date: December 6, 2007Inventors: Jihong Chen, Eddie Hearl Breashears, Xin Wang, John Howard Macpeak
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Publication number: 20070283418Abstract: A system for authenticating access to a data processing device or database is provided. The system includes a comparison module for comparing an attempt identifier with an account identifier, and a state-determining module for determining a state variable associated with at least one of the attempt identifier and the account identifier. The state-determining module determines the state variable by incrementing the state variable if the attempt identifier does not match the account identifier and if the state variable is less than a predetermined upper bound threshold, decrementing the state variable if the attempt identifier does match the account identifier and if the state variable is greater than a predetermined lower bound threshold, and authenticating the attempt identifier if the attempt identifier does match the account identifier and if the state variable equals the predetermined lower bound threshold.Type: ApplicationFiled: February 1, 2006Publication date: December 6, 2007Applicant: Florida Atlantic UniversityInventors: Jihong Chen, Sam Hsu, Saeed Rajput
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Patent number: 7129582Abstract: A method of forming a semiconductor device includes implanting a precipitate into a gate conductor of an at least partially formed semiconductor device. The gate conductor including a plurality of semiconductor grains. The boundaries of adjacent grains forming a dopant migration path. A plurality of precipitate regions are formed within the gate conductor. At least some of the precipitate regions located at a junction of at least two grains. The gate conductor of the at least partially formed semiconductor device is doped with a dopant. The dopant diffuses inwardly along the dopant migration path.Type: GrantFiled: July 15, 2005Date of Patent: October 31, 2006Assignee: Texas Instruments IncorporatedInventors: Kaiping Liu, Zhiqiang Wu, Jihong Chen
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Publication number: 20060163651Abstract: The present invention provides a method for manufacturing a transistor device, a method for manufacturing an integrated circuit, and a transistor device. The method for manufacturing the transistor device, among other steps, includes forming a gate structure over a substrate and forming source/drain regions in the substrate proximate the gate structure, the source/drain regions having a boundary that forms an electrical junction with the substrate. The method further includes forming dislocation loops in the substrate, the dislocation loops not extending outside the boundary of the source/drain regions.Type: ApplicationFiled: January 25, 2005Publication date: July 27, 2006Applicant: Texas Instruments, IncorporatedInventors: Antonio Rotondaro, Kaiping Liu, Jihong Chen, Amitabh Jain
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Publication number: 20050263897Abstract: A method of forming a semiconductor device includes implanting a precipitate into a gate conductor of an at least partially formed semiconductor device. The gate conductor including a plurality of semiconductor grains. The boundaries of adjacent grains forming a dopant migration path. A plurality of precipitate regions are formed within the gate conductor. At least some of the precipitate regions located at a junction of at least two grains. The gate conductor of the at least partially formed semiconductor device is doped with a dopant. The dopant diffuses inwardly along the dopant migration path.Type: ApplicationFiled: July 15, 2005Publication date: December 1, 2005Inventors: Kaiping Liu, Zhiqiang Wu, Jihong Chen
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Patent number: 6955980Abstract: A method of forming a semiconductor device includes implanting a precipitate into a gate conductor of an at least partially formed semiconductor device. The gate conductor including a plurality of semiconductor grains. The boundaries of adjacent grains forming a dopant migration path. A plurality of precipitate regions are formed within the gate conductor. At least some of the precipitate regions located at a junction of at least two grains. The gate conductor of the at least partially formed semiconductor device is doped with a dopant. The dopant diffuses inwardly along the dopant migration path.Type: GrantFiled: August 30, 2002Date of Patent: October 18, 2005Assignee: Texas Instruments IncorporatedInventors: Kaiping Liu, Zhiqiang Wu, Jihong Chen
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Publication number: 20050212041Abstract: A method of forming an associated transistor is presented whereby short channel effects and junction capacitances are mitigated and enhanced switching speeds are thereby facilitated. Compensation regions are formed within a substrate by implanting dopants relatively deeply over source and drain regions formed within the substrate. The compensation regions are spaced apart slightly less than are the source and drain regions. This spacing affects potential contours and reduces junction capacitances within the transistor. The different distances between the source and drain regions and the compensation regions are achieved by forming and selectively adjusting sidewall spacers adjacent to a gate structure of the transistor. These spacers serve as guides for the dopants implanted into the substrate to form the source and drain regions and the compensation regions.Type: ApplicationFiled: May 11, 2005Publication date: September 29, 2005Inventors: Zhiqiang Wu, Jihong Chen, Kaiping Liu
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Patent number: 6940137Abstract: The present invention provides a semiconductor device 200 having an angled compensation implant, a method of manufacture therefore and a method of manufacturing an integrated circuit including the angled compensation implant. In one embodiment, the method of manufacturing the semiconductor device 200 includes creating a halo implant 240 in a substrate 210, introducing a compensation implant 260 in the substrate 210 at an angle abnormal to the substrate 210 and forming a source/drain region 250 above the compensation implant 260, the angle reducing a capacitance associated with the halo implant 240 or the source/drain region 250. The method further includes placing a gate structure 230 over the substrate 210.Type: GrantFiled: September 19, 2003Date of Patent: September 6, 2005Assignee: Texas Instruments IncorporatedInventors: Jihong Chen, Zhiqiang Wu, Kaiping Liu
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Patent number: 6913980Abstract: A method of forming an associated transistor is presented whereby short channel effects and junction capacitances are mitigated and enhanced switching speeds are thereby facilitated. Compensation regions are formed within a substrate by implanting dopants relatively deeply over source and drain regions formed within the substrate. The compensation regions are spaced apart slightly less than are the source and drain regions. This spacing affects potential contours and reduces junction capacitances within the transistor. The different distances between the source and drain regions and the compensation regions are achieved by forming and selectively adjusting sidewall spacers adjacent to a gate structure of the transistor. These spacers serve as guides for the dopants implanted into the substrate to form the source and drain regions and the compensation regions.Type: GrantFiled: June 30, 2003Date of Patent: July 5, 2005Assignee: Texas Instruments IncorporatedInventors: Zhiqiang Wu, Jihong Chen, Kaiping Liu
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Publication number: 20050062103Abstract: The present invention provides a semiconductor device 200 having an angled compensation implant, a method of manufacture therefore and a method of manufacturing an integrated circuit including the angled compensation implant. In one embodiment, the method of manufacturing the semiconductor device 200 includes creating a halo implant 240 in a substrate 210, introducing a compensation implant 260 in the substrate 210 at an angle abnormal to the substrate 210 and forming a source/drain region 250 above the compensation implant 260, the angle reducing a capacitance associated with the halo implant 240 or the source/drain region 250. The method further includes placing a gate structure 230 over the substrate 210.Type: ApplicationFiled: September 19, 2003Publication date: March 24, 2005Applicant: Texas Instruments, IncorporatedInventors: Jihong Chen, Zhiqiang Wu, Kaiping Liu
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Publication number: 20040266121Abstract: A method of forming an associated transistor is presented whereby short channel effects and junction capacitances are mitigated and enhanced switching speeds are thereby facilitated. Compensation regions are formed within a substrate by implanting dopants relatively deeply over source and drain regions formed within the substrate. The compensation regions are spaced apart slightly less than are the source and drain regions. This spacing affects potential contours and reduces junction capacitances within the transistor. The different distances between the source and drain regions and the compensation regions are achieved by forming and selectively adjusting sidewall spacers adjacent to a gate structure of the transistor. These spacers serve as guides for the dopants implanted into the substrate to form the source and drain regions and the compensation regions.Type: ApplicationFiled: June 30, 2003Publication date: December 30, 2004Inventors: Zhiqiang Wu, Jihong Chen, Kaiping Liu
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Publication number: 20040043543Abstract: A method of forming a semiconductor device includes implanting a precipitate into a gate conductor of an at least partially formed semiconductor device. The gate conductor including a plurality of semiconductor grains. The boundaries of adjacent grains forming a dopant migration path. A plurality of precipitate regions are formed within the gate conductor. At least some of the precipitate regions located at a junction of at least two grains. The gate conductor of the at least partially formed semiconductor device is doped with a dopant. The dopant diffuses inwardly along the dopant migration path.Type: ApplicationFiled: August 30, 2002Publication date: March 4, 2004Applicant: Texas Instruments IncorporatedInventors: Kaiping Liu, Zhiqiang Wu, Jihong Chen
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Patent number: 6064759Abstract: An automatic inspection method and apparatus using structured light and machine vision cameras to inspect an object in conjunction with the geometric model of the object is disclosed. Camera images of the object are analyzed by computer to produce the location of points on the object's surfaces in three dimensions. During a setup phase before object inspection, the points are analyzed with respect to the geometric model computer file of the object. Many points are eliminated to reduce data-taking and analysis time to a minimum and to prevent extraneous reflections from producing errors. When similar objects are subsequently inspected, points from each surface of interest are spatially averaged to give high accuracy measurements of object dimensions. The inspection device uses several multiplexed sensors, each composed of a camera and a structured light source, to measure all sides of the object on a single pass. Calibration and compensation methods are also disclosed.Type: GrantFiled: November 6, 1997Date of Patent: May 16, 2000Inventors: B. Shawn Buckley, Jihong Chen, Dao Shan Yang, Hui Cheng Zhou
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Patent number: 6060372Abstract: A semiconductor device (10) of the present invention has a gate (32) insulatively disposed above the substrate, source and drain regions (36, 38) disposed near the surface in the substrate adjacent opposite sides of the gate (32), and a field oxide region (26) disposed in the surface of the substrate surrounding the source and drain regions (36, 38) and defining an active moat region (20). The channel stop region (24) is disposed below the field oxide region (26) and is spaced from the active moat region (20) with a predetermined spacing.Type: GrantFiled: March 21, 1997Date of Patent: May 9, 2000Assignee: Texas Instruments IncorporatedInventors: Michael C. Smayling, Alister C. Young, John A. Rodriguez, Jihong Chen