Abstract: A method for reducing computer system power consumption. The computer system includes a memory module having a plurality of address pins, and a chipset having a plurality of driving units for driving the address pins. The method includes obtaining number of required address pins by detecting a capacity of the memory module, and disabling the driving units so as to make a number of the active driving units substantially equal to the number of the required address pins.

Abstract: A method for reducing computer system power consumption. The computer system includes a memory module having a plurality of address pins, and a chipset having a plurality of driving units for driving the address pins. The method includes obtaining number of required address pins by detecting a capacity of the memory module, and disabling the driving units so as to make a number of the active driving units substantially equal to the number of the required address pins.

Abstract: A chipset has a plurality of driving units, each unit connecting to an address pin of a memory module for driving a one-bit address signal while accessing the memory module. The method detects configurations of memory modules, and determines which address pins are unused and makes corresponding driving units stop driving to reduce power consumption of unused address pins.

Abstract: A method and related apparatus for performing error checking-correcting (ECC). The method divides a memory space provided by a memory into an ECC range and a non-ECC range. When data is read or written, the method determines the address of data is within the ECC range or the non-ECC range so as to decide whether error checking-correcting is performed on the data.

Abstract: A method for data error checking includes accessing a plurality of sets of data, each of the sets of data having a plurality of bits; integrating the plurality of sets of data into integral data; generating error checking data according to the integral data, the error checking data being changed following any change of the plurality of sets of data; dividing the error checking data into a plurality of sets of sub-checking data, each set of sub-checking data corresponding to one of the plurality of sets of data; and when transmitting each of the plurality of sets of data in order, transmitting the corresponding sub-checking data in the meantime.

Abstract: A method for arbitrating a bus grant among a plurality of master devices for access to a shared bus is disclosed. The method includes the steps of starting to accumulatively count time in response to a data transfer request signal outputted by one of the master devices for requesting a data transfer, and re-estimating a bus-utility condition for the one of the master devices to access to the shared bus when a preset threshold value of time is counted up. In addition, an arbiter for a bus grant among a plurality of master devices for access to a shared bus is disclosed. The arbiter is characterized by including a plurality of timer devices in communication with the plurality of master devices, respectively.

Abstract: A method and related apparatus for performing error checking-correcting (ECC). The method divides a memory space provided by a memory into an ECC range and a non-ECC range. When data is read or written, the method determines the address of data is within the ECC range or the non-ECC range so as to decide whether error checking-correcting is performed on the data.

Abstract: A chipset has a plurality of driving units, each unit connecting to an address pin of a memory module for driving a one-bit address signal while accessing the memory module. The method detects configurations of memory modules, and determines which address pins are unused and makes corresponding driving units stop driving to reduce power consumption of unused address pins.

Abstract: A method for data error checking includes accessing a plurality of sets of data, each of the sets of data having a plurality of bits; integrating the plurality of sets of data into integral data; generating error checking data according to the integral data, the error checking data being changed following any change of the plurality of sets of data; dividing the error checking data into a plurality of sets of sub-checking data, each set of sub-checking data corresponding to one of the plurality of sets of data; and when transmitting each of the plurality of sets of data in order, transmitting the corresponding sub-checking data in the meantime.

Abstract: A computer system includes a monitor, a memory and a processing unit. The monitor includes a main area for displaying an image. The main area has a plurality of rows and a plurality of columns of tiles. Each tile has a plurality of rows and a plurality of columns of display units, and each display unit is for displaying a portion of the image according to corresponding pixel data. The memory includes a plurality of first sequential memory units and a plurality of second sequential memory units. The first sequential memory units are for storing pixel data of a first tile. The second sequential memory units are for storing pixel data of a second tile. The second tile is horizontally next to the first tile. The processing unit sequentially transmits pixel data of pixels in the first tile before transmitting pixel data of pixels in the second tile.

Abstract: A multi-monitor system includes a first and a second monitors, a graphics chipset and an AGP unit. The graphics chipset is integrated therein a graphics processing unit electrically connected to the first monitor and transmits: a first image signal to the first monitor for display. The AGP unit is electrically connected to the graphics chipset and the second monitor, receives a second image signal from the graphics chipset and transmit the second image signal to the second monitor for display.

Abstract: A display system and a driving method thereof. The display system has a display panel, a storage device, a frame buffer, a display controller, a driving circuit, and a digital-to-analog converter. The storage device is used to store display data corresponding to a plurality of pixels of the display panel. The display controller generates the display data and stores the display data in the frame buffer. When data stored in a second memory unit of the frame buffer are different from data stored in a first memory unit of the storage device, the display controller transmits data stored in the second memory unit toward the driving circuit for using the driving circuit to update data stored in the first memory unit. In addition, the digital-to-analog converter then immediately drives a corresponding pixel according to the updated data of the first memory unit.

Abstract: The present invention generally relates to a circuit configuration of a chip and, more particularly to a circuit configuration of a chip with a graphic controller integrated and a method for testing such a circuit configuration, in which a test circuit is employed in a main control module such that a graphic controller is directly connected to a plurality of buses in a testing mode. Thus, the testing of the graphic controller is independent of the main controller module. Moreover, the testing requests are transmitted to the graphic controller by using frequency multiplying modes, and at least one multiplexer and at least one latch are used at the memory end, so that the required pin count for testing is lowered in the present invention.

Abstract: A method for accessing image data is used in a computer system. The computer system includes a core logic unit, a system memory, a graphics accelerator, and an image data outputting device in communication with a south bridge chip of the core logic unit. The method comprises the following steps. Firstly, image data are received from the image data outputting device by the core logic unit. Then, the image data are written into an AGP memory block of the system memory. Afterwards, the image data are accessed in the AGP memory block by the graphics accelerator.

Abstract: A computer system includes a monitor, a memory and a processing unit. The monitor includes a main area for displaying an image. The main area has a plurality of rows and a plurality of columns of tiles. Each tile has a plurality of rows and a plurality of columns of display units, and each display unit is for displaying a portion of the image according to corresponding pixel data. The memory includes a plurality of first sequential memory units and a plurality of second sequential memory units. The first sequential memory units are for storing pixel data of a first tile. The second sequential memory units are for storing pixel data of a second tile. The second tile is horizontally next to the first tile. The processing unit sequentially transmits pixel data of pixels in the first tile before transmitting pixel data of pixels in the second tile.

Abstract: A method for arbitrating a bus grant among a plurality of master devices for access to a shared bus is disclosed. The method includes the steps of starting to accumulatively count time in response to a data transfer request signal outputted by one of the master devices for requesting a data transfer, and re-estimating a bus-utility condition for the one of the master devices to access to the shared bus when a preset threshold value of time is counted up. In addition, an arbiter for a bus grant among a plurality of master devices for access to a shared bus is disclosed. The arbiter is characterized by including a plurality of timer devices in communication with the plurality of master devices, respectively.

Abstract: The present invention generally relates to a circuit configuration of a chip and, more particularly to a circuit configuration of a chip with a graphic controller integrated and a method for testing such a circuit configuration, in which a test circuit is employed in a main control module such that a graphic controller is directly connected to a plurality of buses in a testing mode. Thus, the testing of the graphic controller is independent of the main controller module. Moreover, the testing requests are transmitted to the graphic controller by using frequency multiplying modes, and at least one multiplexer and at least one latch are used at the memory end, so that the required pin count for testing is lowered in the present invention.

Abstract: A device to fit existing engines for the purpose of increasing compressed fuel-mixture pressure and promoting a compression ratio of the fuel-mixture in an engine to enable the fuel-mixture to burn more perfectly and the engine to works more efficiently.In the prior application of the same petitioner, titled "Pressure Addible Engine" with the same purpose to the invention but built in an unit engine which shall request people to throw the used engine away. In incentive of that, present invention modifies the prior invention into independent device unit, suitably fit to existing gasoline engine or diesel engine and makes the invention to be acceptable popularly.