Abstract: A switching of direct deposit payment destination account with a single action is initiated by a user of a finance service. A server system receives user information from a client system, assigns a client identifier to the client system, and associates the assigned client identifier with the received user information. The server system sends to the client system the assigned client identifier and information identifying the employer for one or more direct deposit payment and including a switch button. The client system receives and stores the assigned client identifier and receives and displays the information to the user. In response to activation of the switch button, the client system sends to the server system a request to switch the identified payment to the financial services account information on the server system. The server system generates a direct deposit switching request in accordance with the requirements of the employer.

Abstract: The present disclosure provides systems and methods for nucleic acid sequence analysis. A system for processing raw nucleic acid sequence data from a genomic sequencer comprises a data processing server having a housing contained therein one or more processing modules. The one or more processing modules can each comprise an electronic control unit programmed to align nucleic acid sequence data from a genomic sequencing device and perform one or more of variant analysis and structural variant analysis on the nucleic acid sequence data. The system can further comprise a computer server in communication with the processing server. The computer server can be programmed or otherwise configured to process and/or analyze the aligned nucleic acid sequence data.

Abstract: The present invention describes methods for performing large-scale graph traversal calculations on parallel processor platforms. The invention describes methods for on-the-fly hypothesis rescoring that utilizes graphic processing units (GPUs) in combination with utilizing central processing units (CPUs) of computing devices. The invention is described in one embodiment as applied to the task of large vocabulary continuous speech recognition.

Abstract: The present invention describes methods for performing large-scale graph traversal calculations on parallel processor platforms. The invention describes methods for on-the-fly hypothesis rescoring that utilizes graphic processing units (GPUs) in combination with utilizing central processing units (CPUs) of computing devices. The invention is described in one embodiment as applied to the task of large vocabulary continuous speech recognition.

Abstract: A method of optimizing the calculation of matching scores between phone states and acoustic frames across a matrix of an expected progression of phone states aligned with an observed progression of acoustic frames within an utterance is provided. The matrix has a plurality of cells associated with a characteristic acoustic frame and a characteristic phone state. A first set and second set of cells that meet a threshold probability of matching a first phone state or a second phone state, respectively, are determined. The phone states are stored on a local cache of a first core and a second core, respectively. The first and second sets of cells are also provided to the first core and second core, respectively. Further, matching scores of each characteristic state and characteristic observation of each cell of the first set of cells and of the second set of cells are calculated.

Abstract: A method of optimizing the calculation of matching scores between phone states and acoustic frames across a matrix of an expected progression of phone states aligned with an observed progression of acoustic frames within an utterance is provided. The matrix has a plurality of cells associated with a characteristic acoustic frame and a characteristic phone state. A first set and second set of cells that meet a threshold probability of matching a first phone state or a second phone state, respectively, are determined. The phone states are stored on a local cache of a first core and a second core, respectively. The first and second sets of cells are also provided to the first core and second core, respectively. Further, matching scores of each characteristic state and characteristic observation of each cell of the first set of cells and of the second set of cells are calculated.

Abstract: The present disclosure provides systems and methods for nucleic acid sequence analysis. A system for processing raw nucleic acid sequence data from a genomic sequencer comprises a data processing server having a housing contained therein one or more processing modules. The one or more processing modules can each comprise an electronic control unit programmed to align nucleic acid sequence data from a genomic sequencing device and perform one or more of variant analysis and structural variant analysis on the nucleic acid sequence data. The system can further comprise a computer server in communication with the processing server. The computer server can be programmed or otherwise configured to process and/or analyze the aligned nucleic acid sequence data.

Abstract: Methods for faster statistical inference in computation based recognition problems on highly parallel processors with multiple cores on-a-chip are disclosed, which include: selectively flattening levels of the recognition network to improve inference speed (improving the recognition model); selectively duplicating parts of the recognition network to minimize a critical section in atomic accesses to as few as one atomic instruction (improving the recognition procedure); and combining weight and source port into one 32-bit word to minimize the number of atomic operations. These methods have been implemented on an NVIDIA GTX 280 processor in a Large Vocabulary Continuous Speech Recognition (LVCSR) embodiment, and achieve more than a 10× speed up compared to a highly optimized sequential implementation on an Intel Core i7 processor.

Abstract: Methods for faster statistical inference in computation based recognition problems on highly parallel processors with multiple cores on-a-chip are disclosed, which include: selectively flattening levels of the recognition network to improve inference speed (improving the recognition model); selectively duplicating parts of the recognition network to minimize a critical section in atomic accesses to as few as one atomic instruction (improving the recognition procedure); and combining weight and source port into one 32-bit word to minimize the number of atomic operations. These methods have been implemented on an NVIDIA GTX 280 processor in a Large Vocabulary Continuous Speech Recognition (LVCSR) embodiment, and achieve more than a 10× speed up compared to a highly optimized sequential implementation on an Intel Core i7 processor.

Abstract: Methods and apparatus for implementing Brownian Bridge algorithm on Single Instruction Multiple Data (SIMD) computing platforms are described. In one embodiment, a memory stores a plurality of data corresponding to an SIMD (Single Instruction, Multiple Data) instruction. A processor may include a plurality of SIMD lanes. Each of the plurality of the SIMD lanes may process one of the plurality of data stored in the memory in accordance with the SIMD instruction. Other embodiments are also described.

Abstract: In one embodiment, a processor comprises a register file, register management logic coupled to the register file, and at least two sources of window swap operations coupled to the register management logic. The register management logic is configured to control an interface to the register file to switch register windows in the register file in response to one or more window swap operations. The sources of window swap operations and the register management logic are configured to cooperate according to an arbitration scheme to arbitrate between conflicting window swap operations to be performed using the interface. In one particular implementation, for example, block signals may be used from higher priority sources to lower priority sources to block issuance of window swap operations by the lower priority sources.

Abstract: An apparatus and method for sharing a functional unit. In one embodiment, a processor may include instruction fetch logic configured to issue instructions, and a first functional unit configured to execute instructions issued from the instruction fetch logic and to execute operations issued from a second functional unit, where the operations are issued asynchronously with respect to the instructions. The second functional unit may be configured to provide one or more operands corresponding to a given operation to the first functional unit. The first functional unit may include temporary result storage configured to store a result of the given operation while the first functional unit executes a given instruction issued from the instruction fetch logic, and the first functional unit may be further configured to use the stored result as an operand of an operation issued subsequently to the given operation.