Patents by Inventor Jill C. Hildreth

Jill C. Hildreth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8242564
    Abstract: A semiconductor structure having a transistor region and an optical device region includes a transistor in a first semiconductor layer of the semiconductor structure, wherein the first semiconductor layer is over a first insulating layer, the first insulating layer is over a second semiconductor layer, and the second semiconductor layer is over a second insulating layer. A gate dielectric of the transistor is in physical contact with a top surface of the first semiconductor layer, and the transistor is formed in the transistor region of the semiconductor structure. A waveguide device in the optical device region and a third semiconductor layer over a portion of the second semiconductor layer.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: August 14, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gregory S. Spencer, Jill C. Hildreth, Robert E. Jones
  • Patent number: 8093084
    Abstract: A method for forming a semiconductor structure having a transistor region and an optical device region includes forming a transistor in and on a first semiconductor layer of the semiconductor structure, wherein the first semiconductor layer is over a first insulating layer, the first insulating layer is over a second semiconductor layer, and the second semiconductor layer is over a second insulating layer, wherein a gate dielectric of the transistor is in physical contact with a top surface of the first semiconductor layer, and wherein the transistor is formed in the transistor region of the semiconductor structure. The method also includes forming a waveguide device in the optical device region, wherein forming the waveguide device includes exposing a portion of the second semiconductor layer in the optical device region; and epitaxially growing a third semiconductor layer over the exposed portion of the second semiconductor layer.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: January 10, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gregory S. Spencer, Jill C. Hildreth, Robert E. Jones
  • Publication number: 20110223706
    Abstract: A photodetector is formed to have a germanium detector on a waveguide. The germanium detector has a first surface on the waveguide and a second surface that, when exposed to ambient conditions, forms germanium oxide. In a processing platform, an oxygen-free plasma is applied to the second surface. The oxygen-free plasma removes oxygen that is bonded to germanium at the second surface. A cap layer is formed on the second surface prior to removing the germanium detector from the processing platform.
    Type: Application
    Filed: March 10, 2010
    Publication date: September 15, 2011
    Inventors: JILL C. HILDRETH, Stanley M. Filipiak, Marc A. Rossow, Gregory S. Spencer, Bret T. Wilkerson
  • Publication number: 20100276735
    Abstract: A method for forming a semiconductor structure having a transistor region and an optical device region includes forming a transistor in and on a first semiconductor layer of the semiconductor structure, wherein the first semiconductor layer is over a first insulating layer, the first insulating layer is over a second semiconductor layer, and the second semiconductor layer is over a second insulating layer, wherein a gate dielectric of the transistor is in physical contact with a top surface of the first semiconductor layer, and wherein the transistor is formed in the transistor region of the semiconductor structure. The method also includes forming a waveguide device in the optical device region, wherein forming the waveguide device includes exposing a portion of the second semiconductor layer in the optical device region; and epitaxially growing a third semiconductor layer over the exposed portion of the second semiconductor layer.
    Type: Application
    Filed: April 30, 2009
    Publication date: November 4, 2010
    Inventors: Gregory S. Spencer, Jill C. Hildreth, Robert E. Jones
  • Patent number: 7544997
    Abstract: A method for forming a semiconductor device includes forming a recess in a source region and a recess in a drain region of the semiconductor device. The method further includes forming a first semiconductor material layer in the recess in the source region and a second semiconductor material layer in the recess in the drain region, wherein each of the first semiconductor material layer and the second semiconductor material layer are formed using a stressor material having a first ratio of an atomic concentration of a first element and an atomic concentration of a second element, wherein the first element is silicon and a first level of concentration of a doping material. The method further includes forming additional semiconductor material layers overlying the first semiconductor material layer and the second semiconductor material layer that have a different ratio of the atomic concentration of the first element and the second element.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: June 9, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Da Zhang, Veeraraghavan Dhandapani, Darren V. Goedeke, Jill C. Hildreth
  • Publication number: 20080197412
    Abstract: A method for forming a semiconductor device includes forming a recess in a source region and a recess in a drain region of the semiconductor device. The method further includes forming a first semiconductor material layer in the recess in the source region and a second semiconductor material layer in the recess in the drain region, wherein each of the first semiconductor material layer and the second semiconductor material layer are formed using a stressor material having a first ratio of an atomic concentration of a first element and an atomic concentration of a second element, wherein the first element is silicon and a first level of concentration of a doping material. The method further includes forming additional semiconductor material layers overlying the first semiconductor material layer and the second semiconductor material layer that have a different ratio of the atomic concentration of the first element and the second element.
    Type: Application
    Filed: February 16, 2007
    Publication date: August 21, 2008
    Inventors: Da Zhang, Veeraraghavan Dhandapani, Darren V. Goedeke, Jill C. Hildreth