Abstract: A dynamic clock switching circuit in which a multiplexer (MUX) is connected to clock A and clock B. MUX control lines are encoded to signal clock A or clock B. A MUX control change detector is connected to the multiplexer and to the MUX control lines. A MUX control change detector decodes the MUX control lines and asserts a MUX change signal upon a condition that a change from one clock to another is signaled. A Hold Sync flip-flop is connected to a hold output of a Hold Start flip-flop. The Hold Sync flip-flop is connected to and clocked by the clock A. A Hold Disable flip-flop is connected to an OK to change output of the Hold Sync flip-flop. The Hold Disable flip-flop is connected to and clocked by clock A. A Clock Sync flip-flop is connected to a hold disable output of the Hold Disable flip-flop. A reset input of the Hold Start flip-flop is connected to a clock sync output of the Clock Sync flip-flop. An AND is connected to the hold output and to the hold disable output.