Abstract: A target processor utilizing a feedback loop to maintain a constant false alarm rate for variable level video input signals with noise or noise plus clutter on the input signal. The processor includes three serially connected stages of binary coincidence detectors which comprise a threshold detector for processing video signals which exceed a threshold level, an M of N detector for providing an alarm for each range gate having a count of M or greater pulses, and a P of Q detector for generating a target alarm after at least P or greater frequencies have been transmitted.