Abstract: A portable wireless system for providing a user with access to a computer-based system includes a BARB Badge to interface with the user's body, responsive to a disruption in the interface and including a transceiver to communicate with an external source, a BARB Base to detect a presence of said BARB Badge in a vicinity of said BARB Base and relay secure communications between said BARB Badge and said computer-based system; and an administrator subsystem to regulate interfacing operations of said BARB Badge and said computer-based system based on predetermined administrative protocols. In this way, the overall security of the computer-based system is enhanced while the amount of operational burdens associated with accessing the computer-based system are reduced.

Abstract: A portable wireless system for providing a user with access to a computer-based system includes a BARB Badge to interface with the user's body, responsive to a disruption in the interface and including a transceiver to communicate with an external source, a BARB Base to detect a presence of said BARB Badge in a vicinity of said BARB Base and relay secure communications between said BARB Badge and said computer-based system; and an administrator subsystem to regulate interfacing operations of said BARB Badge and said computer-based system based on predetermined administrative protocols. In this way, the overall security of the computer-based system is enhanced while the amount of operational burdens associated with accessing the computer-based system are reduced.

Abstract: A central processing unit capable of executing the IBM System/370 Universal Instruction Set is disclosed. The instruction set establishes the functional specifications for the processing unit, features of which include: 8-bit (byte) alphanumeric coding, 4-bit packed decimal coding (2 digits per byte), two's complement fixed-point binary arithmetic, two levels of indexing, sixteen 32-bit (4 byte) addressable general registers, four 64-bit floating point registers, and program status word and control registers. Principal features of the hardware architecture include the use of a single main data/instruction bus, transfers to and from the main bus being made under encoded microprogram control, and placement of the fixed-point binary arithmetic logic unit elements and the associated sixteen general registers on a single cascaded group of LSIC chips which operate under control of the microcode.

Abstract: A dynamic address translation unit for converting virtual or "logical" address values into real or "physical" address values. A translation Lookaside Buffer (TLB) stores physical addresses corresponding to a limited number of previously translated logical addresses. The available space in the TLB is divided into partitions, each of which stores address translation data for a particular user process. The TLB partition in current use is identified by the value stored in a user partition counter, which is also used to verify that certain process control information (stored in a stack memory location) associated with the partition matches the process control information for that user process which is currently in control of the central processing unit.

Abstract: A cabinet for a central processing unit, made up of a card cage and refrigeration unit, for mounting and cooling electronic components on a group of vertically-aligned, closely-spaced circuit boards. A source of recirculating, forced, refrigerated air is employed to remove the heat from the highly concentrated electronic components. For ease of maintenance, the refrigeration unit and the power supply unit take the form of independently removable modules, and the removable circuit boards are mounted in a readily accessable card cage which incorporates formed card guides which facilitate card removal and insertion.