Abstract: A method, apparatus, and computer instructions for leasing a unique digital item in a network data processing system. A listing request is received for a payment and a deposit in the account of a first party. A listing request is received for a unique digital item in the account of a second party. Responsive to receiving the listing requests, the respective digital properties are transferred to a temporary storage account in association with retrieval tags. Listings for the digital properties appear on a trusted third-party leasing service. A lease contract is drawn up between the parties. After all parties have signed the lease agreement, the payment is transferred to the second party and the unique digital item is transferred to the first party. The deposit is held by the trusted third-party leasing service until the unique digital item is returned.

Abstract: A method, apparatus, and computer instructions for transferring a unique digital item in a network data processing system. A request to transfer a unique digital item from a source account on a source data processing system to a target account on a target data processing system is received. The transfer request includes the unique digital item and an identification of the target account. A determination is made as to whether the request is valid in response to receiving the request. In response to the request being valid, a transfer of the unique digital item to the target account in the second data processing system is attempted. Responsive to a successful transfer of the unique digital item to the target account, the unique digital item is deleted from the source account in the source data processing system.

Abstract: A signal transmission structure is provided. The structure comprises a reference plane, a bonding pad, a conductive trace and a conductive ball. By changing the shapes of the reference plane and the conductive trace, the equivalent capacitance at the conductive ball and the signal route near thereto is reduced, or the equivalent inductance at the conductive ball and the signal route near thereto is increased to compensate the high equivalent capacitance between the conductive ball and the reference plane. Therefore, the impedance of the conductive ball and the signal route near thereto are matched to increase the integrity of the signals after these signals pass through the conductive ball and the signal neighbor route thereto.

Abstract: An inductor includes a first wiring layer, a second wiring layer, a first conductive trace, a second conductive trace, a third conductive trace, and a fourth conductive trace. The first conductive trace is on the first wiring layer and the second conductive trace is on the second wiring layer. The third conductive trace is parallel to the first conductive trace and is on the first wiring layer. The fourth conductive trace is parallel to the second conductive trace- and is on the second wiring layer. The first end of the first conductive trace is connected to the first end of the second conductive trace through a first via plug. The second end of the second conductive trace is connected to the first end of the third conductive trace through a second via plug. The second end of the third conductive trace is connected to the first end of the fourth conductive trace through a third via plug.

Abstract: The present invention is to provide a structure of multi-tier wire bonding for high frequency integrated circuits. The structure comprises a first electronic device, a second electronic device and a plurality of metal wires. The first electronic device has a first bonding surface, a first carrying surface and a first grouping of bonding pads. The first grouping of bonding pads is distributed surrounding the border of the first bonding surface, and the first grouping of bonding pads at least can be divided into the first row and the second row bonding pads. The second electronic device has the second carrying surface and a plurality of second grouping of bonding pads. The second carrying surface is abutted against the first carrying surface for carrying the first electronic device, such that the first electronic device and the second electronic device overlap one another.

Abstract: A printed circuit transformer includes a first wiring layer, a second wiring layer, a primary conductive coil including a first conductive trace, a second conductive trace, a third conductive trace, and a fourth conductive trace, which are on the first wiring layer or the second wiring layer, a first via plug, a second via plug, and a third via plug for connecting the ends of the conductive traces in the primary conductive coil, and a secondary conductive coil including a fifth conductive trace, a sixth conductive trace, a seventh conductive trace, and a eighth conductive trace, which are on the first wiring layer or the second wiring layer, a fourth via plug, a fifth via plug, and a sixth via plug for connecting the ends of the conductive traces in the secondary conductive coil.

Abstract: A flip-chip package substrate layout for reducing plan inductance. The flip-chip package substrate includes a plurality of sequentially stacked wiring layers, at least one insulation layer between two neighboring wiring layers so that the insulation layer and the wiring layers are alternately stacked on top of each other, and a plurality of conductive plugs individually penetrating the insulation layer for electrically connecting the wiring layers. The uppermost wiring layer has at least one power pad region, which has a plurality of power bump pads, while the bottommost wiring layer has a plurality of bonding pads. The position of the power pad region maybe interchanged with the neighboring ground pad region. In addition, two ends of the power pad region may also be extended toward the ground pad region. Hence, the power bump pads located at the two ends of the power pad region are respectively electrically connected to one of the bonding pads through the wiring layers and the conductive plugs.

Abstract: A flip-chip package substrate comprising a plurality of wiring layers, at least one insulation layers and at least one conductive plugs. The wiring layers are sequentially stacked such that an insulation layer is always sandwiched between two neighboring wiring layers. The conductive plug passes through the insulation layer for connecting with wiring layers. The uppermost wiring layer has a plurality of bump pads while the bottommost wiring layer has a plurality of ball pads. The bump pads on the uppermost wiring layer are organized into bump pad rings. Similarly, the ball pads on the bottommost wiring layer are organized into ball pad rings. Relative position of both the bump pad rings and the ball pad rings are organized according to functions in sequential order so that the wiring distance from the bump pads down to the ball pads is optimized.

Abstract: A chip package structure with a guard circuit design. The individual wires of two pairs of ground wires are positioned on each side of a high frequency signal wire so that external interference is minimized during transmission, multiple ground contacts are provided and current routes are shortened. In the meantime, strength of the electromagnetic field produced by the high frequency signal wire during transmission is limited within the pairs of ground wires. Ultimately, the range of interference by the electromagnetic field, the insertion loss and the return loss are all reduced resulting in improved performance of the chip package.

Abstract: A flip-chip package substrate layout for reducing plan inductance. The flip-chip package substrate includes a plurality of sequentially stacked wiring layers, at least one insulation layer between two neighboring wiring layers so that the insulation layer and the wiring layers are alternately stacked on top of each other, and a plurality of conductive plugs individually penetrating the insulation layer for electrically connecting the wiring layers. The uppermost wiring layer has at least one power pad region, which has a plurality of power bump pads, while the bottommost wiring layer has a plurality of bonding pads. The position of the power pad region maybe interchanged with the neighboring ground pad region. In addition, two ends of the power pad region may also be extended toward the ground pad region. Hence, the power bump pads located at the two ends of the power pad region are respectively electrically connected to one of the bonding pads through the wiring layers and the conductive plugs.

Abstract: A flip-chip package substrate comprising a plurality of wiring layers, at least one insulation layers and at least one conductive plugs. The wiring layers are sequentially stacked such that an insulation layer is always sandwiched between two neighboring wiring layers. The conductive plug passes through the insulation layer for connecting with wiring layers. The uppermost wiring layer has a plurality of bump pads while the bottommost wiring layer has a plurality of ball pads. The bump pads on the uppermost wiring layer are organized into bump pad rings. Similarly, the ball pads on the bottommost wiring layer are organized into ball pad rings. Relative position of both the bump pad rings and the ball pad rings are organized according to functions in sequential order so that the wiring distance from the bump pads down to the ball pads is optimized.

Abstract: A multi-layered substrate having a voltage reference signal circuit layout therein. A major change in the design of the multi-layered substrate is the moving of a voltage reference signal trace from a signal layer to a non-signaling layer. Once the voltage reference signal trace is moved, the signal traces within the signal layer can have a larger layout area. Similarly, the voltage reference signal trace within the non-signaling layer can have greater layout flexibility in addition to electromagnetic shielding from other signal traces. Moreover, the voltage reference signal trace having a greater width may be used to reduce parasitic resistance within the voltage reference signal circuit.