Abstract: A device includes a communications circuit configured to communicate with a storage device controller and a host device. The device further includes a processing device configured to receive a request from the storage device controller through the communications circuit. The request requests encrypted data be written to a memory address of the host device. The processing device is further configured to identify a key associated with the write request based on the memory address. The processing device is further configured to generate a decrypted version of the data based on the key. The processing device is further configured to initiate transfer, through the communications circuit, of the decrypted version of the data to the host device.

Abstract: A device includes a communications circuit configured to communicate with a storage device controller and a host device. The device further includes a processing device configured to receive a request from the storage device controller through the communications circuit. The request requests encrypted data be written to a memory address of the host device. The processing device is further configured to identify a key associated with the write request based on the memory address. The processing device is further configured to generate a decrypted version of the data based on the key. The processing device is further configured to initiate transfer, through the communications circuit, of the decrypted version of the data to the host device.

Abstract: A device includes a communications circuit configured to communicate with a storage device controller and a host device. The device further includes a processing device configured to receive a request from the storage device controller through the communications circuit. The request requests encrypted data be written to a memory address of the host device. The processing device is further configured to identify a key associated with the write request based on the memory address. The processing device is further configured to generate a decrypted version of the data based on the key. The processing device is further configured to initiate transfer, through the communications circuit, of the decrypted version of the data to the host device.

Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include flash memory storage to store data, a volatile memory storage, and a host interface layer to receive requests from a host machine. An SSD controller may manage reading data from and writing data to the flash memory storage, with a flash translation layer to translate between Logical Block Addresses and Physical Block Addresses, a flash memory controller to access the flash memory storage, a volatile memory controller to access the volatile memory storage, and an orchestrator to send instructions to a Data Movement Interconnect (DMI). The DMI may include at least two kernels, a Buffer Manager, a plurality of ring agents associated with the kernels and the Buffer Manager to handle messaging, a Data Movement Manager (DMM) to manage data movement, at least two data rings to move data between the ring agents, and a control ring to share commands and acknowledgments between the ring agents and the DMM.

Abstract: A device includes a communications circuit configured to communicate with a storage device controller and a host device. The device further includes a processing device configured to receive a request from the storage device controller through the communications circuit. The request requests encrypted data be written to a memory address of the host device. The processing device is further configured to identify a key associated with the write request based on the memory address. The processing device is further configured to generate a decrypted version of the data based on the key. The processing device is further configured to initiate transfer, through the communications circuit, of the decrypted version of the data to the host device.

Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include flash memory storage to store data, a volatile memory storage, and a host interface layer to receive requests from a host machine. An SSD controller may manage reading data from and writing data to the flash memory storage, with a flash translation layer to translate between Logical Block Addresses and Physical Block Addresses, a flash memory controller to access the flash memory storage, a volatile memory controller to access the volatile memory storage, and an orchestrator to send instructions to a Data Movement Interconnect (DMI). The DMI may include at least two kernels, a Buffer Manager, a plurality of ring agents associated with the kernels and the Buffer Manager to handle messaging, a Data Movement Manager (DMM) to manage data movement, at least two data rings to move data between the ring agents, and a control ring to share commands and acknowledgments between the ring agents and the DMM.

Abstract: Some embodiments include a communication hub for presenting audio-visual data from electronic devices. Other embodiments of related systems and methods are disclosed.

Abstract: Some embodiments include a communication hub for presenting audio-visual data from electronic devices. Other embodiments of related systems and methods are disclosed.

Abstract: In some examples, a control system comprises a first unit and a second unit. The first unit comprises a command input configured to receive one or more commands from one or more command devices of a command device array, and a first transceiver configured to transmit one or more encoded commands. The second unit second unit comprises a second transceiver configured to receive the one or more encoded commands from the first transceiver, and a command output configured to output one or more decoded commands to a content source array. The first and second units are separate from each other. The one or more encoded commands correspond to the one or more commands, the one or more decoded commands correspond to the one or more encoded commands, and the content source array comprises one or more content sources. Other examples and related methods are described herein.

Abstract: A multiple-core, multithreaded processor including a flexible error steering mechanism. An integrated circuit may include processor cores. Each processor core is associated with a respective number of threads and is configured to issue a first instruction from one of the threads during one execution cycle and a second instruction from another one of the threads during a successive execution cycle. An error processing unit may be coupled to the processor cores and configured to detect an error condition corresponding to a data element external to the processor cores. In response to detecting the error condition, the error processing unit may convey an indication of the error to a selected processor core dependent upon an identifier of the selected core. The error indication may also include an identifier of a selected thread executable on the selected processor core. The identifiers of the selected core and the selected thread may be programmable.

Abstract: A wireless transmission system is provided. The wireless transmission system can include: (a) a receiver unit capable of being coupled to a display device; and (b) a transmitter unit that sends a wireless signal to the receiver unit, wherein the wireless signal comprises a bandwidth sufficient enough to carry high definition video content. Other embodiments are disclosed.