Abstract: A memory apparatus, includes: a memory including memory regions; a table storing a memory address and a number of reading times of data; a first buffer storing first data from another memory apparatus and a first memory address of the first data; a second buffer storing second data to the another memory apparatus and a second memory address of the second data; and a controller configured to store, when a first number of reading times being minimum in the table is smaller than a second number of reading times of the first data, the first data and the first memory address into the first buffer and outputs third data in a memory region of the first number and a third memory address of the third data to the another memory apparatus via the second buffer, and rewrites the third data and memory address with the first data and memory address.

Abstract: A memory device includes a storage unit in which a plurality of semiconductor chips each comprising a plurality of memory blocks respectively arranged in a planar direction and a plurality of redundant blocks respectively arranged in a planar direction are stacked, a detecting unit configured to detect a defect of each of the memory blocks in the storage unit; a checking unit configured to check free capacity in each of the redundant blocks in the storage unit, and a determining unit configured to determine a substitute block to be substituted for the memory block in which the defect has been detected from the redundant blocks having the free capacity.

Abstract: A memory apparatus, includes: a memory including memory regions; a table storing a memory address and a number of reading times of data; a first buffer storing first data from another memory apparatus and a first memory address of the first data; a second buffer storing second data to the another memory apparatus and a second memory address of the second data; and a controller configured to store, when a first number of reading times being minimum in the table is smaller than a second number of reading times of the first data, the first data and the first memory address into the first buffer and outputs third data in a memory region of the first number and a third memory address of the third data to the another memory apparatus via the second buffer, and rewrites the third data and memory address with the first data and memory address.

Abstract: An electronic device includes: a nonvolatile memory; a volatile memory stacked over the nonvolatile memory; and a controller configured to store setting information of the volatile memory in the nonvolatile memory before cutting off power supply to the volatile memory, and to set the setting information stored in the nonvolatile memory to the volatile memory after resuming power supply to the volatile memory.

Abstract: A semiconductor memory apparatus includes a memory block to include memory cells to hold data; a precharge control unit to control precharging the memory cells; a row decoder to output a row selection signal identifying a row address of the memory cells; an integral circuit to integrate a signal level of the row selection signal for a same row address, and to have an integral characteristic where an integral value of the signal level becomes a predetermined value when the row selection signal for the same row address is consecutively output for a predetermined number of times; and a determination unit to determine whether the integral value of the integral circuit becomes the predetermined value or greater. The precharge control unit turns off precharging the memory cells when the integral value of the integral circuit becomes the predetermined value or greater.

Abstract: A memory device includes a storage unit in which a plurality of semiconductor chips each comprising a plurality of memory blocks respectively arranged in a planar direction and a plurality of redundant blocks respectively arranged in a planar direction are stacked, a detecting unit configured to detect a defect of each of the memory blocks in the storage unit; a checking unit configured to check free capacity in each of the redundant blocks in the storage unit, and a determining unit configured to determine a substitute block to be substituted for the memory block in which the defect has been detected from the redundant blocks having the free capacity.

Abstract: A semiconductor memory apparatus includes a memory block to include memory cells to hold data; a precharge control unit to control precharging the memory cells; a row decoder to output a row selection signal identifying a row address of the memory cells; an integral circuit to integrate a signal level of the row selection signal for a same row address, and to have an integral characteristic where an integral value of the signal level becomes a predetermined value when the row selection signal for the same row address is consecutively output for a predetermined number of times; and a determination unit to determine whether the integral value of the integral circuit becomes the predetermined value or greater. The precharge control unit turns off precharging the memory cells when the integral value of the integral circuit becomes the predetermined value or greater.

Abstract: An apparatus includes a nonvolatile memory, an interface that at least receives an erase command of the nonvolatile memory, a first controller that controls the nonvolatile memory to execute data erasing on the basis of the erase command output from the interface, an external input unit which is installed independently of the interface, a second controller that controls the nonvolatile memory to execute data erasing on the basis of an erase instruction signal output from the external input unit, and a change-over circuit that switches between connection of the first controller with the nonvolatile memory and connection of the second controller with the nonvolatile memory, wherein the second controller controls the nonvolatile memory to execute data erasing on the basis of the erase instruction when the connection of the second controller with the nonvolatile memory is established by the change-over circuit.

Abstract: In a semiconductor storage apparatus, an internal address generation unit generates, when receiving successive first and second external addresses, from the second external address an internal address for selecting any of the memory cells connected to bit lines and word lines except the bit line and word line connected to a memory cell to be selected according to the first external address. When receiving the successive external addresses, a memory cell connected to the same bit line and word line is not continuously selected, and erroneous readout due to rewriting of a value of the memory cell in a non-selected state is suppressed.

Abstract: In a semiconductor storage apparatus, an internal address generation unit generates, when receiving successive first and second external addresses, from the second external address an internal address for selecting any of the memory cells connected to bit lines and word lines except the bit line and word line connected to a memory cell to be selected according to the first external address. When receiving the successive external addresses, a memory cell connected to the same bit line and word line is not continuously selected, and erroneous readout due to rewriting of a value of the memory cell in a non-selected state is suppressed.

Abstract: An apparatus includes a nonvolatile memory, an interface that at least receives an erase command of the nonvolatile memory, a first controller that controls the nonvolatile memory to execute data erasing on the basis of the erase command output from the interface, an external input unit which is installed independently of the interface, a second controller that controls the nonvolatile memory to execute data erasing on the basis of an erase instruction signal output from the external input unit, and a change-over circuit that switches between connection of the first controller with the nonvolatile memory and connection of the second controller with the nonvolatile memory, wherein the second controller controls the nonvolatile memory to execute data erasing on the basis of the erase instruction when the connection of the second controller with the nonvolatile memory is established by the change-over circuit.

Abstract: A memory device that can include a power-supply voltage detector that detects power-supply voltage values and that outputs a detection result indicating which power-supply voltage value is detected; a data-rate setter that sets data rates corresponding to the detection result of the power-supply voltage detector, in synchronization with a rising edge or falling edge of a clock signal; and a memory cell array that performs reading/writing at the data rates set by the data-rate setter.

Abstract: A memory device that can include a power-supply voltage detector that detects power-supply voltage values and that outputs a detection result indicating which power-supply voltage value is detected; a data-rate setter that sets data rates corresponding to the detection result of the power-supply voltage detector, in synchronization with a rising edge or falling edge of a clock signal; and a memory cell array that performs reading/writing at the data rates set by the data-rate setter.

Abstract: A switch station including an ATM switch; a memory storing control data for operations of the switch station; an intra-station device, accommodating a subscriber line, performing communication operation on subscriber ATM cell; a control processor generating control information in link access protocol (LAP) format; and an interface unit converting LAP control information into ATM cell to the intra-station device through the ATM switch, wherein the control information is communicated according to LAP, the intra-station device receives the control information and transmits a direct memory access request to obtain control data stored in the memory, the interface unit obtains and converts the data format of the control data into ATM cell to transmit to the intra-station device through the switch, and the intra-station device performs the communication operation on the subscriber ATM cell based on the control data received through the switch.

Abstract: This invention relates to a functional device such as an FPGA carrying out a necessary function by programming, and provides a functional device, a function maintaining method and a function maintaining program which can maintain a function continuously. A plurality of function parts (FPGAs) is provided, and a function is maintained by switching from a function part, in which a failure is occurring, to a function part under stand-by. The plurality of function parts, a failure detection part (failure detection circuits) and a switching part (switching circuits) are provided, and a function part under operation and a function part under stand-by a reset. That is, the function part in which the failure is occurring is made into a stand-by state, and the function part which is under stand-by is made to operate.

Abstract: A circuit board having a mount part onto which the electronic component is mounted includes a plurality of wiring patterns at least one of which is electrically connectible to one of a plurality of first terminals of an electronic component, the plurality of first terminals being hidden by the electronic component once the electronic component is mounted onto the mount part, a pair of second terminals that expose around a mount part, one of the pair of second terminals being one-by-one connected to each first terminal, the other of the pair of second terminals being connected to each wiring pattern, and a signal line that exposes around the mount part and electrically connects the pair of second terminals to each other.

Abstract: This invention relates to a functional device such as an FPGA carrying out a necessary function by programming, and provides a functional device, a function maintaining method and a function maintaining program which can maintain a function continuously. A plurality of function parts (FPGAs) is provided, and a function is maintained by switching from a function part, in which a failure is occurring, to a function part under stand-by. The plurality of function parts, a failure detection part (failure detection circuits) and a switching part (switching circuits) are provided, and a function part under operation and a function part under stand-by a reset. That is, the function part in which the failure is occurring is made into a stand-by state, and the function part which is under stand-by is made to operate.

Abstract: The quality and performance of the connectionless communications system are improved. When a BOM is received, the destination address DA of the L3-PDU stored in the payload of the BOM is retrieved, and the tag information is obtained from the DA (S11). The output message identifier MID is reserved (S12), and the tag information and output MID are assigned to the BOM (S13). Then, the tag information and output MID are written to the table. When a COM is received, the tag information and output MID are retrieved using the MID of the COM as a key, and the information is provided for the COM (S31 and S32). When an EOM is received, the tag information and output MID are retrieved using the MID of the EOM as a key, and the information is provided for the EOM (S41 and S42). Then, the output MID is released (S43).

Abstract: The quality and performance of the connectionless communications system are improved. When a BOM is received, the destination address DA of the L3-PDU stored in the payload of the BOM is retrieved, and the tag information is obtained from the DA (S11). The output message identifier MID is reserved (S12), and the tag information and output MID are assigned to the BOM (S13). Then, the tag information and output MID are written to the table. When a COM is received, the tag information and output MID are retrieved using the MID of the COM as a key, and the information is provided for the COM (S31 and S32). When an EOM is received, the tag information and output MID are retrieved using the MID of the EOM as a key, and the information is provided for the EOM (S41 and S42). Then, the output MID is released (S43).

Abstract: Source data is stored in a source data storage unit and a comparing device compares source data with destination data stored in a destination data storage unit. A destination address compressing unit compresses destination address information, and other accounting parameters are output with some delay. An accumulating device accumulates information from the destination address compressing unit as an address. A source address compressing unit compresses or delays information from an accumulating unit, and then outputs information. A source address carrier compressing unit compresses or delays information from the source address compressing unit, and then outputs information. A destination address source address carrier re-compressing unit compresses or delays compressed information from the source address carrier compressing unit, and then outputs information. A period abnormality detecting circuit in an accounting unit validates transfer data and prevents a wrong accounting process from being performed.