Patents by Inventor Jin Cai

Jin Cai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170227485
    Abstract: An exemplary biosensor sensor for detecting the presence of a biological material includes an SOI substrate, a BJT formed on at least a portion of the substrate, and a sensing structure formed on at least a portion of an upper surface of the BJT. The BJT includes an emitter region, a collector region and a self-aligned epitaxially grown intrinsic base region laterally adjacent to the emitter and collector regions. The sensing structure includes an opening, centered above and exposing the intrinsic base region, and at least one dielectric layer formed in the opening and contacting at least a portion of the intrinsic base region. The dielectric layer is configured to respond to charges in biological molecules.
    Type: Application
    Filed: February 9, 2016
    Publication date: August 10, 2017
    Inventors: Jin Cai, Tak H. Ning, Jeng-Bang Yau, Sufi Zafar
  • Patent number: 9726631
    Abstract: An exemplary biosensor sensor for detecting the presence of a biological material includes an SOI substrate, a BJT formed on at least a portion of the substrate, and a sensing structure formed on at least a portion of an upper surface of the BJT. The BJT includes an emitter region, a collector region and a self-aligned epitaxially grown intrinsic base region laterally adjacent to the emitter and collector regions. The sensing structure includes an opening, centered above and exposing the intrinsic base region, and at least one dielectric layer formed in the opening and contacting at least a portion of the intrinsic base region. The dielectric layer is configured to respond to charges in biological molecules.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: August 8, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Tak H. Ning, Jeng-Bang Yau, Sufi Zafar
  • Patent number: 9691886
    Abstract: A method of forming a semiconductor structure includes providing an emitter and a collector on a surface of an insulator layer. The emitter and the collector are spaced apart and have a doping of a first conductivity type. An intrinsic base is formed between the emitter and the collector and on the insulator layer by epitaxially growing the intrinsic base from at least a vertical surface of the emitter and a vertical surface of the collector. The intrinsic base has a doping of a second conductivity type opposite to the first conductivity type, and a first heterojunction exists between the emitter and the intrinsic base and a second heterojunction exists between the collector and the intrinsic base.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: June 27, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Kevin K. Chan, Christopher P. D'Emic, Tak H. Ning, Jeng-Bang Yau
  • Patent number: 9666267
    Abstract: A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge that is injected to the charge storage element may be used to adjust the threshold voltage (Vt) of each of the semiconductor devices within an array of semiconductor devices that are present on the substrate.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: May 30, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jin Cai, Kangguo Cheng, Robert H. Dennard, Ali Khakifirooz, Tak H. Ning
  • Patent number: 9647099
    Abstract: A method of forming a semiconductor structure includes providing an emitter and a collector on a surface of an insulator layer. The emitter and the collector are spaced apart and have a doping of a first conductivity type. An intrinsic base is formed between the emitter and the collector and on the insulator layer by epitaxially growing the intrinsic base from at least a vertical surface of the emitter and a vertical surface of the collector. The intrinsic base has a doping of a second conductivity type opposite to the first conductivity type, and a first heterojunction exists between the emitter and the intrinsic base and a second heterojunction exists between the collector and the intrinsic base.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: May 9, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Kevin K. Chan, Christopher P. D'Emic, Tak H. Ning, Jeng-Bang Yau
  • Patent number: 9625409
    Abstract: An exemplary biosensor sensor for detecting the presence of a biological material includes an SOI substrate, a lateral BJT formed on at least a portion of the substrate, and a sensing structure formed on at least a portion of an upper surface of the BJT. The BJT includes an emitter region, a collector region and a base region, the base region being formed between the emitter and collector regions and laterally adjacent thereto. The sensing structure includes at least one dielectric layer contacting at least a portion of the base region. The dielectric layer forms a receptacle for confining a biological molecule being tested and is configured to respond to charges in biological molecules, the charges being converted to a sensing signal by the BJT.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: April 18, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Tak H. Ning, Jeng-Bang Yau, Sufi Zafar
  • Publication number: 20170092749
    Abstract: After forming a trench extending through an insulator layer and an underlying top semiconductor portion that is comprised of a first semiconductor material and a dopant of a first conductivity type to define an emitter and a collector on opposite sides of the trench in the top semiconductor portion, an intrinsic base comprising a second semiconductor material having a bandgap less than a bandgap of the first semiconductor material and a dopant of a second conductivity type opposite the first conductivity type is formed in a lower portion the trench by selective epitaxial growth. The intrinsic base protrudes above the top semiconductor portion and is laterally surrounded by entire top semiconductor portion and a portion of the insulator layer. An extrinsic base is then formed on top of the intrinsic base to fill a remaining volume of the trench by a deposition process.
    Type: Application
    Filed: September 28, 2015
    Publication date: March 30, 2017
    Inventors: Jin Cai, Kevin K. Chan, Christopher P. D'Emic, Tak H. Ning, Jeng-Bang Yau
  • Patent number: 9564429
    Abstract: An integrated sensor for detecting the presence of an environmental material and/or condition includes a sensing structure and first and second bipolar junction transistors (BJTs). The first BJT has a base that is electrically coupled with the sensing structure and is configured to generate an output signal indicative of a change in stored charge in the sensing structure. The second BJT is configured to amplify the output signal of the first bipolar junction transistor. The first and second BJTs and the sensing structure are monolithically formed a common substrate.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: February 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Tak H. Ning, Jeng-Bang Yau, Sufi Zafar
  • Publication number: 20170004873
    Abstract: A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge that is injected to the charge storage element may be used to adjust the threshold voltage (Vt) of each of the semiconductor devices within an array of semiconductor devices that are present on the substrate.
    Type: Application
    Filed: September 15, 2016
    Publication date: January 5, 2017
    Inventors: Jin Cai, Kangguo Cheng, Robert H. Dennard, Ali Khakifirooz, Tak H. Ning
  • Publication number: 20170005085
    Abstract: A method of forming a semiconductor structure includes depositing a high-k dielectric layer within a first recess located between sidewall spacers of a first CMOS device and within a second recess located between sidewall spacers of a second CMOS device. A dummy titanium nitride layer is deposited on the high-k dielectric layer. Next, the high-k dielectric layer and the dummy titanium nitride layer are removed from the second recess in the second CMOS device. A silicon cap layer is deposited within the first recess and the second recess, the silicon cap layer is located above the high-k dielectric layer and dummy titanium nitride layer in the first CMOS device. Subsequently, dopants are implanted into the silicon cap layer located in the second recess of the second CMOS device.
    Type: Application
    Filed: September 14, 2016
    Publication date: January 5, 2017
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Jin Cai, Effendi Leobandung, Tak H. Ning
  • Publication number: 20160379975
    Abstract: An integrated sensor for detecting the presence of an environmental material and/or condition includes a sensing structure and first and second bipolar junction transistors (BJTs). The first BJT has a base that is electrically coupled with the sensing structure and is configured to generate an output signal indicative of a change in stored charge in the sensing structure. The second BJT is configured to amplify the output signal of the first bipolar junction transistor. The first and second BJTs and the sensing structure are monolithically formed a common substrate.
    Type: Application
    Filed: June 25, 2015
    Publication date: December 29, 2016
    Inventors: Jin Cai, Tak H. Ning, Jeng-Bang Yau, Sufi Zafar
  • Patent number: 9520660
    Abstract: A socket device includes a socket mounted on a circuit board and an engaging member mounted to the socket. The socket defines a sliding groove. The engaging member includes a sliding piece engaged in the sliding groove. The sliding piece can slide along the slot to detach the engaging member from the socket. A chip may be mounted below the engaging member which member may be moved away from the socket to enable user to check the chip.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: December 13, 2016
    Assignees: HONG FU JIN PRECISION INDUSTRY (WuHan) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Ching-Jou Chen, Shen-Fa Tsai, Jie Li, Jin-Cai Gao
  • Patent number: 9502504
    Abstract: Lateral SOI bipolar transistor structures are provided including an intrinsic base semiconductor material portion in which all surfaces of the intrinsic base not forming an interface with either a collector semiconductor material portion or an emitter semiconductor material portion, contain an extrinsic base semiconductor material portion. Each extrinsic base semiconductor material portion is of the same conductivity type as that of the intrinsic base semiconductor material portion, yet each extrinsic base semiconductor material portion has a higher dopant concentration than the intrinsic base semiconductor material portion. The intrinsic base semiconductor material portion of the lateral SOI bipolar transistors of the present application does not have any interface with surrounding insulator material layers. As such, any potential charge build-up in the surrounding insulator material layers is shielded by the extrinsic base semiconductor material portions.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: November 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Kevin K. Chan, Tak H. Ning, Jeng-Bang Yau
  • Publication number: 20160322779
    Abstract: After forming a first trench extending through a top semiconductor layer and a buried insulator layer and into a handle substrate of a semiconductor-on-insulator (SOI) substrate, a dielectric waveguide material stack including a lower dielectric cladding layer, a core layer and an upper dielectric cladding layer is formed within the first trench. Next, at least one lateral bipolar junction transistor (BJT), which can be a PNP BJT, an NPN BJT or a pair of complementary PNP BJT and NPN BJT, is formed in a remaining portion of the top semiconductor layer. After forming a second trench extending through the dielectric waveguide material stack to re-expose a portion of a bottom surface of the first trench, a laser diode is formed in the second trench.
    Type: Application
    Filed: July 8, 2016
    Publication date: November 3, 2016
    Inventors: Jin Cai, Effendi Leobandung, Ning Li, Tak H. Ning, Jean-Olivier Plouchart, Devendra K. Sadana
  • Patent number: 9484464
    Abstract: A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge that is injected to the charge storage element may be used to adjust the threshold voltage (Vt) of each of the semiconductor devices within an array of semiconductor devices that are present on the substrate.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: November 1, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jin Cai, Kangguo Cheng, Robert H. Dennard, Ali Khakifirooz, Tak H. Ning
  • Patent number: 9478534
    Abstract: A method of forming a semiconductor structure includes depositing a high-k dielectric layer within a first recess located between sidewall spacers of a first CMOS device and within a second recess located between sidewall spacers of a second CMOS device. A dummy titanium nitride layer is deposited on the high-k dielectric layer. Next, the high-k dielectric layer and the dummy titanium nitride layer are removed from the second recess in the second CMOS device. A silicon cap layer is deposited within the first recess and the second recess, the silicon cap layer is located above the high-k dielectric layer and dummy titanium nitride layer in the first CMOS device. Subsequently, dopants are implanted into the silicon cap layer located in the second recess of the second CMOS device.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: October 25, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jin Cai, Effendi Leobandung, Tak H. Ning
  • Publication number: 20160300935
    Abstract: A method of forming a semiconductor structure includes providing an emitter and a collector on a surface of an insulator layer. The emitter and the collector are spaced apart and have a doping of a first conductivity type. An intrinsic base is formed between the emitter and the collector and on the insulator layer by epitaxially growing the intrinsic base from at least a vertical surface of the emitter and a vertical surface of the collector. The intrinsic base has a doping of a second conductivity type opposite to the first conductivity type, and a first heterojunction exists between the emitter and the intrinsic base and a second heterojunction exists between the collector and the intrinsic base.
    Type: Application
    Filed: December 30, 2015
    Publication date: October 13, 2016
    Inventors: Jin Cai, Kevin K. Chan, Christopher P. D'Emic, Tak H. Ning, Jeng-Bang Yau
  • Publication number: 20160300934
    Abstract: A method of forming a semiconductor structure includes providing an emitter and a collector on a surface of an insulator layer. The emitter and the collector are spaced apart and have a doping of a first conductivity type. An intrinsic base is formed between the emitter and the collector and on the insulator layer by epitaxially growing the intrinsic base from at least a vertical surface of the emitter and a vertical surface of the collector. The intrinsic base has a doping of a second conductivity type opposite to the first conductivity type, and a first heterojunction exists between the emitter and the intrinsic base and a second heterojunction exists between the collector and the intrinsic base.
    Type: Application
    Filed: April 13, 2015
    Publication date: October 13, 2016
    Inventors: Jin Cai, Kevin K. Chan, Christopher P. D'Emic, Tak H. Ning, Jeng-Bang Yau
  • Publication number: 20160276807
    Abstract: After forming a first trench extending through a top semiconductor layer and a buried insulator layer and into a handle substrate of a semiconductor-on-insulator (SOI) substrate, a dielectric waveguide material stack including a lower dielectric cladding layer, a core layer and an upper dielectric cladding layer is formed within the first trench. Next, at least one lateral bipolar junction transistor (BJT), which can be a PNP BJT, an NPN BJT or a pair of complementary PNP BJT and NPN BJT, is formed in a remaining portion of the top semiconductor layer. After forming a second trench extending through the dielectric waveguide material stack to re-expose a portion of a bottom surface of the first trench, a laser diode is formed in the second trench.
    Type: Application
    Filed: March 19, 2015
    Publication date: September 22, 2016
    Inventors: Jin Cai, Effendi Leobandung, Ning Li, Tak H. Ning, Jean-Olivier Plouchart, Devendra K. Sadana
  • Patent number: 9450381
    Abstract: After forming a first trench extending through a top semiconductor layer and a buried insulator layer and into a handle substrate of a semiconductor-on-insulator (SOI) substrate, a dielectric waveguide material stack including a lower dielectric cladding layer, a core layer and an upper dielectric cladding layer is formed within the first trench. Next, at least one lateral bipolar junction transistor (BJT), which can be a PNP BJT, an NPN BJT or a pair of complementary PNP BJT and NPN BJT, is formed in a remaining portion of the top semiconductor layer. After forming a second trench extending through the dielectric waveguide material stack to re-expose a portion of a bottom surface of the first trench, a laser diode is formed in the second trench.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: September 20, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jin Cai, Effendi Leobandung, Ning Li, Tak H. Ning, Jean-Olivier Plouchart, Devendra K. Sadana