Abstract: A clock tree syntheses (CTS) tool designs a group of clock trees to be incorporated into an IC design for conveying separate clock signals to clock sinks within the IC with a predetermined maximum group skew. The tool initially generates a separate, independently balanced, first clock tree design for each clock tree and then processes each first clock tree design to estimate an average path delay of the clock signal it conveys to each sink. The CTS tool then selects, as a target path delay, a highest average delay from among average delays computed for all clock trees. Thereafter the CTS tool generates a separate second clock tree design for each clock tree that is balanced to limit a difference between the target path delay and an estimated delay to each sink to a value that ensures a group clock skew will reside within the predetermined maximum group skew.

Abstract: A method is disclosed for synthesizing a clock tree for a partitioned integrated circuit (IC) layout comprising a plurality of base level partitions and a top level partition each occupying a separate area of a semiconductor substrate. The base level partitions include syncs to be clocked by edges of a clock signal applied to an entry node within the area occupied by the top level partition. In accordance with the method, a plurality of independently balanced subtrees are separately synthesized. Each subtree resides within the area occupied by a separate base level partition and includes a start point at a perimeter of the area occupied by that base level partition and a network of buffers and signal paths for conveying a clock signal edge from the start point to each sync included within that area. Thereafter a top level portion of the clock tree is synthesized.

Abstract: A system, method, and program for remotely interacting with a diagnostic interface resident on wireless computer devices. The wireless device provides an accessible diagnostic interface that allows reads and/or writes to device resident diagnostic data and tools. Through use of the interaction, wireless device status data and network status data can be gathered and utilized, and if so embodied, the diagnostic tools resident on the wireless devices can be manipulated to alter wireless device operation.

Abstract: An integrated circuit (IC) layout system initially modifies a netlist describing an IC as a hierarchy of circuit modules to combine clusters of cells forming selected modules so that they form a smaller number of larger cells. This reduces the number of cells forming the IC, thereby reducing the time the system needs to generate an IC layout. The system then generates a trial layout of the IC described by the modified netlist. Based on the shape and position of the area each module occupies in the trial layout, the system estimates the shape and position of a substrate area each module would require in a layout where module areas did not overlap. The system then divides the IC design into several partitions, each including separate set of the modules forming the IC, and creates a partition plan allocating substrate space to each partition based on the estimated space requirement of each module assigned to that partition.

Abstract: A method is disclosed for synthesizing a clock tree for a partitioned integrated circuit (IC) layout comprising a plurality of base level partitions and a top level partition each occupying a separate area of a semiconductor substrate, The base level partitions include syncs to be clocked by edges of a clock signal applied to an entry node within the area occupied by the top level partition. In accordance with the method, a plurality of independently balanced subtrees are separately synthesized. Each subtree resides within the area occupied by a separate base level partition and includes a start point at a perimeter of the area occupied by that base level partition and a network of buffers and signal paths for conveying a clock signal edge from the start point to each sync included within that area. Thereafter a top level portion of the clock tree is synthesized.

Abstract: A clock tree syntheses (CTS) tool designs a group of clock trees to be incorporated into an IC design for conveying separate clock signals to clock sinks within the IC with a predetermined maximum group skew. The tool initially generates a separate, independently balanced, first clock tree design for each clock tree and then processes each first clock tree design to estimate an average path delay of the clock signal it conveys to each sink. The CTS tool then selects, as a target path delay, a highest average delay from among average delays computed for all clock trees. Thereafter the CTS tool generates a separate second clock tree design for each clock tree that is balanced to limit a difference between the target path delay and an estimated delay to each sink to a value that ensures a group clock skew will reside within the predetermined maximum group skew.

Abstract: A gated clock tree including a hierarchy of gates is synthesized by separately synthesizing a subtree residing under each gate, starting with the subtrees residing under gates at lowest level of the hierarchy and working upwards though the gate hierarchy. To design a subtree under a selected gate at any given level of the gate hierarchy, a centroid of a set of all downstream sinks and gates residing at a next lower level of the hierarchy that are to receive the clock signal via the selected gate is initially determined. A set of subtree endpoints are then established, each residing between the centroid and a corresponding sink or gate of the set of downstream sinks and gates. A balanced subtree is then designed to convey the clock signal from the selected gate to each subtree endpoint, and a separate signal path is designed to convey the clock signal from each subtree endpoint to a corresponding downstream sink or gate of the set.

Abstract: When generating a layout for an integrated; circuit (IC) based on a netlist design, a trial layout which need only satisfy the various spatial, power and other constraints, but need not satisfy the layout's timing constraints, is quickly produced. The trial layout acts as a basis for estimating sizes and positions of substrate areas needed to accommodate various modules of the IC and for estimating delays through various signal paths having timing constraints. After producing the trial layout, the IC design is divided into several partitions with modules being grouped into partitions in accordance with their proximity to one another in the trial layout. A floor plan is created which imposes spatial constraints on each partition based on the estimated size and position within the trial layout of the modules forming the partition. A timing budget is also created which allocates portions of each timing constraint to the partitions based on the time delay estimates derived from the trial layout.

Abstract: A system and method for determining timing offset errors in a low earth orbit satellite system based upon Doppler and Doppler rate of change is provided. A user terminal determines first and second timing offsets respectively associated with first and second satellite beams from respective first and second satellites. Next, the user terminal determines the Doppler and Doppler rate of change associated with the first and second satellite beams. A timing offset is estimated from the measured Doppler and Doppler rate of change and is then compared with the user terminal's own determined timing offset. If the comparison does not produce a value within a predetermined threshold, a beam identification error is declared.

Abstract: An integrated circuit (IC) layout system initially modifies a netlist describing an IC as a hierarchy of circuit modules to combine clusters of cells forming selected modules so that they form a smaller number of larger cells. This reduces the number of cells forming the IC, thereby reducing the time the system needs to generate an IC layout. The system then generates a trial layout of the IC described by the modified netlist. Based on the shape and position of the area each module occupies in the trial layout, the system estimates the shape and position of a substrate area each module would require in a layout where module areas did not overlap. The system then divides the IC design into several partitions, each including separate set of the modules forming the IC, and creates a partition plan allocating substrate space to each partition based on the estimated space requirement of each module assigned to that partition.

Abstract: When generating a layout for an integrated circuit (IC) based on a netlist design, a trial layout which need only satisfy the various spatial, power and other constraints, but need not satisfy the layout's timing constraints, is quickly produced. The trial layout acts as a basis for estimating sizes and positions of substrate areas needed to accommodate various modules of the IC and for estimating delays through various signal paths having timing constraints. After producing the trial layout, the IC design is divided into several partitions with modules being grouped into partitions in accordance with their proximity to one another in the trial layout. A floor plan is created which imposes spatial constraints on each partition based on the estimated size and position within the trial layout of the modules forming the partition. A timing budget is also created which allocates portions of each timing constraint to the partitions based on the time delay estimates derived from the trial layout.

Abstract: Disclosed herein is a method for dividing an integrated circuit (IC) design into several circuit partitions, each including one or more circuit modules, and then separately carrying out placement and routing for each circuit partition, with each partition being implemented within a separate area of an IC substrate. The method initially generates a whole-chip trial placement that tends to cluster cells of each circuit module together. An IC substrate floor plan assigning modules to various partitions is prepared, with the size, shape and relative position of each partition being determined by size, shape and relative position of areas of the substrate occupied by those modules in the trial floor plan. A trial routing is also performed with information on which to base a pin assignment plan for each module. A detailed placement and routing process is then independently performed for each partition, with placement and routing of cells within each partition constrained by the floor plan and pin assignment plan.

Abstract: An apparatus, method, and process for quickly and accurately determining the position of a user terminal in a satellite communications system. An initial coarse estimate of the radius of the Earth at a terminal position is made. The geometry of satellites being used and the user terminal is then determined. When only one satellite is used, the satellite-user terminal geometry includes the range and range rate of the satellite with respect to the user terminal. When two satellites are used, the satellite-user terminal geometry includes the range of each satellite with respect to the user terminal. An initial position estimate is determined based on the radius and the satellite-user terminal geometry. The coarse radius estimate can then be formed into a fine estimate and the initial position estimate further refined.

Abstract: In computer-aided electronic design automation software, a placement system biases clustering of cells according to their hierarchical design while optimizing placement for controlling die size and total wire length. The placement system also provides for slack distribution, row improvement and randomization during partitioning. Floor plans based on trial placement and placement guiding blocks are also described.

Abstract: The present invention is a system and method for accurately determining the distance (range) between one or more satellites and a user terminal and the rate of change (range rate) of that distance. When accurately determined according to the present invention, these quantities can be used to determine the location of the user terminal with a high degree of accuracy. When one satellite is available, the present invention determines the range and range rate based on the Doppler frequency shift that a signal experiences between the satellite and the user terminal, the round trip delay a signal experiences during transmission from the satellite to the user terminal and back via a satellite to a gateway, the Doppler frequency shift a signal experiences between the satellite and the gateway, and the timestamps of the measurements.

Abstract: A method for optimizing a logical design for emulation. The present invention optimzes latch-based designs by transforming them into a flip-flop based circuit. The design is analyzed to determine whether any consecutive latches are clocked by the same clock signal. If consecutive latches are clocked by the same clock signal, for example, the same phase of the same master clock, a transparency condition exists. Transparent latches are transformed into either a flip-flop/buffer/multiplexer circuit or a buffer circuit depending upon whether the latch in the logic design has an enable input. If consecutive latches in a design are clocked by different clock signals, i.e., different phases of the master clock, no transparency condition exists. Non-transparent latches are transformed into a flip-flop.

Abstract: An emulation system and method that reduces or eliminates the number of timing errors such as hold time violations when implementing a netlist description of an integrated circuit. The emulation system comprises a plurality of reprogrammable logic circuits and a plurality of reprogrammable interconnect circuits. The netlist description is optimized to reduce the number of timing violations by removing the occurences of gated clocks from the netlist, partitioning the netlist description by taking into account the occurence of timing violations and ensuring that retain state nets are implemented properly.