Abstract: An improved computer graphics memory architecture has a frame buffer and a Z buffer, each having a forward and reverse part, each of which is wide enough to handle two pixels of data. A data path is connected to the buffers so that in a 3-D application, a full pixel of both color and Z-value data is transported along the data path in a single I/O transaction. In a 2-D application, two pixels of data are transported along the data path in a single I/O transaction. In a preferred embodiment, both the frame and Z buffers are divided into two parts each wide enough to handle one pixel of data part. In 3-D applications, a data path is selectively connected to the buffers in a manner so that one pixel of color data and one pixel of Z-value data are simultaneously transported to the drawing processor during each I/O transaction. In this preferred embodiment, a first reversing switch such as a multiplexer circuit, is provided to reverse data that arrives from the buffer in reverse order.

Abstract: A method and system for performing 2.sup.n -way interleaving of data words over P memory banks is disclosed. Each of the memory banks is partitioned into 2.sup.n partitions. The data word (pixel) address space is partitioned into P contiguous sequences. Each of the P sequences of data word addresses is associated with a unique group of 2.sup.n partitions. In each group, each partition is in a different memory bank. The data word addresses of each of the P sequences are then interleaved over the associated group of partitions. In interleaving the sequence of data word addresses, the data word addresses are alternately associated with sequential memory addresses in the group of partitions in a round-robin fashion. The method and system are particularly applicable where P is not a power of 2.