Abstract: A display device may include a first touch sensing member on a top surface of a display panel, a second touch sensing member on a bottom surface of the display panel, a main FPCB coupled to the display panel and including first and second connecting portions, a first touch FPCB connected to the first touch sensing member and the first connecting portion, a second touch FPCB connected to the second touch sensing member and the second connecting portion, a first touch driving circuit on the first touch FPCB, and a second touch driving circuit on the second touch FPCB. The first touch driving circuit and the first connecting portion may be positioned opposite to each other with respect to the main FPCB. The second touch driving circuit and the second connecting portion may be positioned opposite to each other with respect to the main FPCB.

Abstract: Methods and apparatus for depositing a cobalt layer in a feature, such as, a word line formed in a substrate, are provided herein. In some embodiments, method of processing a substrate includes: exposing a substrate at a first temperature to a cobalt containing precursor to deposit a cobalt layer within a word line feature formed in the substrate, wherein the word line feature is part of a 3D NAND device; and annealing the substrate to remove contaminants from the cobalt layer and to reflow the cobalt layer into the word line feature, wherein the substrate is at a second temperature greater than the first temperature during the annealing.

Abstract: A backlight assembly includes a plurality of point light sources, a light guide plate (“LGP”) and a printed circuit board (“PCB”). The LGP has a light incident face in which light is incident, a side surface extending from an edge portion of the light incident face, and a fixing groove which is formed from the side surface toward an inner portion thereof. The PCB includes a point light source disposing portion in which the point light sources are disposed along a first direction, an extending portion extending from the point light disposing portion along a second direction substantially perpendicular to the first direction, and a protrusion which is fixed at an end portion of the extending portion. The protrusion of the PCB is coupled with the fixing groove of the LGP.

Abstract: The present invention relates to a sweetener composition for preventing or treating obesity containing, as active ingredients, a glucose or D-fructose absorption inhibiting component and a sugar hydrolysis inhibiting sugar or sugar alcohol.

Abstract: The present invention relates to a sweetener composition for alleviating diabetes, containing psicose and a slowly digestible or digestion-resistant polysaccharide as active ingredients, wherein diabetes alleviating effects and the quality of sweetness are enhanced.

Abstract: A method for manufacturing a semiconductor device, for example formed utilizing component stacking. As non-limiting examples, various aspects of this disclosure provide a method for reducing warpage and/or stress in stacked semiconductor devices.

Abstract: The present invention relates to a fibrous starch with enhanced emulsifying capacity and emulsifying stability, and low-fat mayonnaise and margarine compositions using the same. More specifically, disclosed are fibrous starch which has an increased starch particle size and exhibits improved emulsifying capacity and emulsion stability, prepared by heat-treating starch at a temperature lower than a gelatinization temperature, phosphorylating the starch and further heat-treating the starch sample at a high temperature, and low-fat mayonnaise and margarine compositions in which the content of cooking oil is reduced by 50% or more by adding the fibrous starch with enhanced emulsifying capacity thereto.

Abstract: A method for a semiconductor device utilizing redistribution layers to couple stacked die is disclosed and may include bonding a first semiconductor die to a second semiconductor die, the first semiconductor die having a first surface comprising bond pads, a second surface opposite the first surface that is bonded to a first surface of the second semiconductor die, and sloped sides surfaces between the first and second surfaces of the first semiconductor die, such that a cross-section of the first semiconductor die is trapezoidal in shape. A passivation layer may be formed on the first surface and sloped side surfaces of the first semiconductor die and the first surface of the second semiconductor die. A redistribution layer may be formed on the passivation layer formed on the first surface and sloped side surfaces of the first semiconductor die and the first surface of the second semiconductor die.

Abstract: A method for a semiconductor device utilizing redistribution layers to couple stacked die is disclosed and may include bonding a first semiconductor die to a second semiconductor die, the first semiconductor die having a first surface comprising bond pads, a second surface opposite the first surface that is bonded to a first surface of the second semiconductor die, and sloped sides surfaces between the first and second surfaces of the first semiconductor die, such that a cross-section of the first semiconductor die is trapezoidal in shape. A passivation layer may be formed on the first surface and sloped side surfaces of the first semiconductor die and the first surface of the second semiconductor die. A redistribution layer may be formed on the passivation layer formed on the first surface and sloped side surfaces of the first semiconductor die and the first surface of the second semiconductor die.

Abstract: Provided is a semiconductor memory device calibrating a termination resistance, the semiconductor memory device comprising self-adjustment logic configured to determine whether a value of an upper bit string of a calibration code generated in response to a calibration start signal is equal to or greater than an upper critical value of the calibration code, or is equal to or less than a lower critical value of the calibration code, and to generate an adjustment signal for adjusting a value of a termination resistance of a data output driver based on the determination result; and resistance calibration logic configured to provide the upper bit string to the self-adjustment logic, and to generate an updated calibration code by performing a calibration calculation based on the calibration code and a comparison signal generated according to a result of comparing a reference voltage and a voltage of a comparison target node.

Abstract: A radiation imaging apparatus and a radiation image display method implemented using the radiation imaging apparatus, may include a display unit to display at least one first radiation image in at least one view area, and a control unit. If the control unit obtains a second radiation image corresponding to a first radiation image selected from the at least one first radiation image, the control unit controls the display unit to display the second radiation image in a view area in which the selected first radiation image is displayed.

Abstract: A semiconductor device utilizing redistribution layers to couple stacked die is disclosed and may include a first semiconductor die with a first surface comprising bond pads, a second surface opposite the first surface, and sloped side surfaces between the first and second surfaces, such that a cross-section of the first die is trapezoidal in shape. A second semiconductor die with a first surface may be bonded to the second surface of the first die, wherein the first surface of the second die may comprise bond pads. A passivation layer may be formed on the first surface and sloped side surfaces of the first die and the first surface of the second die. A redistribution layer may be formed on the passivation layer, electrically coupling bond pads on the first and second die. A conductive pillar may extend from a bond pad on the second die to the second redistribution layer.

Abstract: Provided is a semiconductor memory device calibrating a termination resistance, the semiconductor memory device comprising self-adjustment logic configured to determine whether a value of an upper bit string of a calibration code generated in response to a calibration start signal is equal to or greater than an upper critical value of the calibration code, or is equal to or less than a lower critical value of the calibration code, and to generate an adjustment signal for adjusting a value of a termination resistance of a data output driver based on the determination result; and resistance calibration logic configured to provide the upper bit string to the self-adjustment logic, and to generate an updated calibration code by performing a calibration calculation based on the calibration code and a comparison signal generated according to a result of comparing a reference voltage and a voltage of a comparison target node.

Abstract: The present invention relates to a cracker composition containing xylose, to a cracker made from the composition, and to a method for preparing the composition, wherein xylose is included not only to achieve excellent coloring and gloss even without spraying oils and fats on the surface of the cracker, but to also provide a low-calorie, low-fat cracker with an excellent, light and simple taste. More particularly, the present invention relates to a cracker composition containing xylose, to a cracker made from the composition, and to a method for preparing the composition, wherein the cracker is prepared from a composition that contains xylose rather than spraying oils and fats on the surface of the cracker which would lead to the uptake of a high amount of fat and calories, to thereby provide a cracker which has a superior appearance and olfactory and gustatory characteristic, which is healthy, and which can be used as a snack for weight control.

Abstract: A semiconductor device utilizing redistribution layers to couple stacked die is disclosed and may include a first semiconductor die with a first surface comprising bond pads, a second surface opposite the first surface, and sloped side surfaces between the first and second surfaces, such that a cross-section of the first die is trapezoidal in shape. A second semiconductor die with a first surface may be bonded to the second surface of the first die, wherein the first surface of the second die may comprise bond pads. A passivation layer may be formed on the first surface and sloped side surfaces of the first die and the first surface of the second die. A redistribution layer may be formed on the passivation layer, electrically coupling bond pads on the first and second die. A conductive pillar may extend from a bond pad on the second die to the second redistribution layer.

Abstract: A backlight assembly includes a light source unit including a circuit board, a light source disposed on a first plane of the circuit board, and at least one connection unit disposed on a second plane opposite to the first plane of the circuit board and electrically connected to the light source, a receiving container having a bottom plate and sidewalls extending from edges of the bottom plate and receiving the light source unit, the bottom plate including at least one opening portion in which the connection unit is inserted and exposed to the outside, and at least one driving unit disposed at a rear surface of the receiving container and connected to the connection unit for driving the light source unit.

Abstract: A light emitting diode (“LED”) backlight assembly. The LED backlight assembly has a bottom container which has a bottom plate and a side edge surrounding the bottom plate, a plurality of light emitting diode printed circuit boards (“LED-PCBs”) on the bottom plate, and a connector which is closely located to edge located LEDs. The connector of the LED-PCB is closely located to an LED driving board, which is disposed at a lateral space of a lateral part of the bottom container to limit a vertical thickness of the backlight light assembly.

Abstract: The present invention relates to a sweetener composition for preventing or treating obesity containing, as active ingredients, a glucose or D-fructose absorption inhibiting component and a sugar hydrolysis inhibiting sugar or sugar alcohol.

Abstract: A backlight assembly includes a plurality of point light sources, a light guide plate (“LGP”) and a printed circuit board (“PCB”). The LGP has a light incident face in which light is incident, a side surface extending from an edge portion of the light incident face, and a fixing groove which is formed from the side surface toward an inner portion thereof The PCB includes a point light source disposing portion in which the point light sources are disposed along a first direction, an extending portion extending from the point light disposing portion along a second direction substantially perpendicular to the first direction, and a protrusion which is fixed at an end portion of the extending portion. The protrusion of the PCB is coupled with the fixing groove of the LGP.