Abstract: Discussed is a welding inspection apparatus for battery modules capable of applying an alternating current to a bank constituted by two or more battery cells connected in parallel and a battery module constituted by one or more banks connected in series to calculate an impedance and a resistance value of each of the one or more banks, and a method of inspecting welding of the battery module using the welding inspection apparatus.

Abstract: A plant cultivation method includes the steps of: applying supplementary light treatment to a selected plant with UVA, measuring a maximum quantum yield of the selected plant; and determining a cultivation step of the plant according to the measured maximum quantum yield.

Abstract: The present invention relates to a method for enhancing growth and useful substances of leafy vegetables by using environmental stress. The environmental stress may include a low temperature stress, a light stress, and a combination thereof.

Abstract: A method for promoting growth and bioactive substances of Crepidiastrum denticulatum including performing a stress treatment on Crepidiastrum denticulatum during cultivation thereof, in which the stress treatment includes at least of applying visible light, drying, exposing to low temperature, irradiating ultraviolet rays, and applying a chemical elicitor.

Abstract: A device including a work table having an upper plate elevated from a floor, a cultivation bed disposed on the upper plate and including an accommodation hole to accommodate soil or culturing solution therein, and a flow tube disposed in the soil or culturing solution to supply or drain water to and from the accommodation hole, a supply portion to circulate water in the flow tube to lower the temperature of water, a light emitting portion including a pillar adjustable in height and a UV light source emit UV light toward an upper portion of the cultivation bed, and a power generator including a servo motor disposed below the work table, and a bracket configured to adjust a location of the light emitting portion with respect to the side surface of the work table.

Abstract: A plant cultivation method includes the steps of: applying supplementary light treatment to a selected plant with UVA, measuring a maximum quantum yield of the selected plant; and determining a cultivation step of the plant according to the measured maximum quantum yield.

Abstract: The present invention relates to a method for enhancing growth and useful substances of leafy vegetables by using environmental stress. The environmental stress may include a low temperature stress, a light stress, and a combination thereof.

Abstract: A device for UV and low temperature treatment for increasing a functional material content in a plant including a work table having an upper plate elevated from a floor, a cultivation bed disposed on the upper plate and including an accommodation hole to accommodate soil or culturing solution therein, and a flow tube disposed in the soil or culturing solution to supply or drain water to and from the accommodation hole, a supply portion to circulate water in the flow tube to lower the temperature of water, a light emitting portion including a pillar adjustable in height and a UV light source emit UV light toward an upper portion of the cultivation bed, and a power generator including a servo motor disposed below the work table, and a bracket configured to adjust a location of the light emitting portion with respect to the side surface of the work table.

Abstract: A method for promoting growth and bioactive substances of Crepidiastrum denticulatum including performing a stress treatment on Crepidiastrum denticulatum during cultivation thereof, in which the stress treatment includes at least of applying visible light, drying, exposing to low temperature, irradiating ultraviolet rays, and applying a chemical elicitor.

Abstract: A semiconductor device includes a plurality of semiconductor chips connected through a scribe lane; a plurality of through electrodes formed in each of the plurality of semiconductor chips; a heat dissipation member formed in the scribe lane; and heat transfer members connecting the through electrodes with the heat dissipation member.

Abstract: Disclosed are dual mode beamforming methods and apparatuses for the same. An exemplary embodiment of the dual mode beamforming method may comprise obtaining a boundary equation generated based on mean channel gains (MCGs) and spatial correlation coefficients (SCCs) for a plurality of antennas of a plurality of base station; obtaining, from the plurality of base stations, MCGs of respective antennas equipped in each of the plurality of base stations and a SCC of a plurality of antennas equipped in at least one base station of the plurality of base stations; and determining a beamforming mode based on the boundary equation, the MCGs and SCCs obtained from the plurality of base stations. Therefore, a co-located beamforming or a distributed beamforming can be performed selectively according to a radio communication environment.

Abstract: Disclosed are dual mode beamforming methods and apparatuses for the same. An exemplary embodiment of the dual mode beamforming method may comprise obtaining a boundary equation generated based on mean channel gains (MCGs) and spatial correlation coefficients (SCCs) for a plurality of antennas of a plurality of base station; obtaining, from the plurality of base stations, MCGs of respective antennas equipped in each of the plurality of base stations and a SCC of a plurality of antennas equipped in at least one base station of the plurality of base stations; and determining a beamforming mode based on the boundary equation, the MCGs and SCCs obtained from the plurality of base stations. Therefore, a co-located beamforming or a distributed beamforming can be performed selectively according to a radio communication environment.

Abstract: A stacked semiconductor package includes a first semiconductor chip having one surface, and an other surface which faces away from the one surface, and first through electrodes which pass through the one surface and the other surface and project out of the other surface; a second semiconductor chip stacked over the one surface of the first semiconductor chip and having second through electrodes which are connected with the first through electrodes; a heat dissipation member disposed over the second semiconductor chip; and a first heat absorbing member disposed to face the other surface of the first semiconductor chip and defined with through holes into which projecting portions of the first through electrodes are inserted.

Abstract: A semiconductor chip includes a substrate having one surface and an other surface which substantially faces away from the one surface; at least two alignment bumps formed on the one surface of the substrate and having different diameters; and at least two alignment grooves defined on the other surface of the substrate and having different diameters.

Abstract: A semiconductor device includes a plurality of semiconductor chips connected through a scribe lane; a plurality of through electrodes formed in each of the plurality of semiconductor chips; a heat dissipation member formed in the scribe lane; and heat transfer members connecting the through electrodes with the heat dissipation member.

Abstract: A semiconductor chip includes a semiconductor chip body having a top surface, a bottom surface, and side surfaces. The bottom surface may have a groove pattern defined by removing a partial thickness of the semiconductor chip body to extend from one or more edges of the semiconductor chip body toward a center portion of the semiconductor chip body. Through electrodes may be formed to extend from the top surface of the semiconductor chip body and pass through the groove pattern defined on the bottom surface. A heat dissipation pattern may fill in the groove pattern defined on the bottom surface and may be connected with the through electrodes.

Abstract: A semiconductor chip includes a substrate having one surface and an other surface which substantially faces away from the one surface; at least two alignment bumps formed on the one surface of the substrate and having different diameters; and at least two alignment grooves defined on the other surface of the substrate and having different diameters.

Abstract: A stacked semiconductor package includes a first semiconductor chip having one surface, and an other surface which faces away from the one surface, and first through electrodes which pass through the one surface and the other surface and project out of the other surface; a second semiconductor chip stacked over the one surface of the first semiconductor chip and having second through electrodes which are connected with the first through electrodes; a heat dissipation member disposed over the second semiconductor chip; and a first heat absorbing member disposed to face the other surface of the first semiconductor chip and defined with through holes into which projecting portions of the first through electrodes are inserted.

Abstract: A semiconductor chip includes: a semiconductor substrate in which a bonding pad is provided on a first surface thereof; a through silicon via (TSV) group including a plurality of TSVs connected to the bonding pad and exposed to a second surface opposite to the first surface of the semiconductor substrate; and a fuse box including a plurality of fuses connected to the plurality of TSVs and formed on the first surface of the semiconductor substrate.

Abstract: A semiconductor chip includes a semiconductor chip body having a top surface, a bottom surface, and side surfaces. The bottom surface may have a groove pattern defined by removing a partial thickness of the semiconductor chip body to extend from one or more edges of the semiconductor chip body toward a center portion of the semiconductor chip body. Through electrodes may be formed to extend from the top surface of the semiconductor chip body and pass through the groove pattern defined on the bottom surface. A heat dissipation pattern may fill in the groove pattern defined on the bottom surface and may be connected with the through electrodes.