Patents by Inventor Jin-I LEE
Jin-I LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10559580Abstract: A semiconductor memory device includes insulating patterns and gate patterns alternately stacked on a substrate, a channel structure that intersects the insulating patterns and the gate patterns and connected to the substrate, a charge storage structure between the channel structure and the gate patterns, and a contact structure on the substrate at a side of the insulating patterns and the gate patterns. One of the gate patterns includes a first barrier pattern between a first insulating pattern of the insulating patterns and a second insulating pattern of the insulating patterns adjacent the first insulating pattern in a first direction perpendicular to a main surface of the substrate, the first barrier pattern defining a concave region between a first portion of the first barrier pattern extending along the first insulating pattern and a second portion extending along the second insulating pattern, and a metal pattern in the concave region.Type: GrantFiled: August 25, 2016Date of Patent: February 11, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Hoon Son, Kyunghyun Kim, Byeongju Kim, Phil Ouk Nam, Kwangchul Park, Yeon-Sil Sohn, Jin-I Lee, Wonbong Jung
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Patent number: 10103163Abstract: A semiconductor memory device is disclosed. The device may include a stack including gate electrodes stacked on a substrate in a vertical direction and insulating patterns interposed between the gate electrodes, vertical channels passing through the stack and connected to the substrate, a tunnel insulating layer enclosing each of the vertical channels, charge storing patterns provided between the tunnel insulating layer and the gate electrodes and spaced apart from each other in the vertical direction, blocking insulating patterns provided between the charge storing patterns and the gate electrodes and spaced apart from each other in the vertical direction, and a bit line crossing the stack and connected to the vertical channels. The blocking insulating patterns may have a vertical thickness that is greater than that of the gate electrodes.Type: GrantFiled: August 27, 2016Date of Patent: October 16, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-Hoon Son, Jin-I Lee, Kyunghyun Kim, Byeongju Kim, Phil Ouk Nam, Kwangchul Park, Yeon-Sil Sohn, JongHeun Lim, Wonbong Jung
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Patent number: 10079203Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a vertical direction with respect to a top surface of the substrate, a plurality of non-metal gate patterns surrounding the channels and being stacked on top of each other and spaced apart from each other along the vertical direction, and a plurality of metal gate patterns stacked on top of each other. The metal gate patterns are spaced apart from each other along the vertical direction. Each of the metal gate patterns surrounds a corresponding one of the non-metal gate patterns.Type: GrantFiled: September 21, 2016Date of Patent: September 18, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Hoon Son, Cha-Dong Yeo, Han-Mei Choi, Kyung-Hyun Kim, Phil-Ouk Nam, Kwang-Chul Park, Yeon-Sil Sohn, Jin-I Lee, Won-Bong Jung
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Patent number: 9997534Abstract: A vertical memory device includes a substrate, a channel on the substrate, extending in a vertical direction with respect to a top surface of the substrate, and including a protrusion at a lower portion of the channel, the protrusion extending in a parallel direction with respect to the top surface of the substrate, a semiconductor pattern connecting the protrusion and the substrate, and gate lines stacked and spaced apart from each other in the vertical direction, the gate lines on the protrusion and the semiconductor pattern and surrounding the channel.Type: GrantFiled: May 16, 2016Date of Patent: June 12, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Hoon Son, Kyung-Hyun Kim, Byeong-Ju Kim, Phil-Ouk Nam, Kwang Chul Park, Yeon-Sil Sohn, Jin-I Lee, Jong-Heun Lim, Won-Bong Jung, Kohji Kanamori
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Patent number: 9905568Abstract: A nonvolatile memory device includes a conductive line disposed on a substrate and vertically extended from the substrate, a first channel layer disposed on the substrate and vertically extended from the substrate, wherein the first channel layer is spaced apart from the conductive line, a second channel layer vertically extended from the substrate, wherein the second channel layer is disposed between the first channel layer and the conductive line, a first gate electrode disposed between the conductive line and the second channel layer, wherein the first gate electrode includes a first portion having a first thickness and a second portion having a second thickness that is different from the first thickness, and a second gate electrode disposed between the first channel layer and the second channel layer, wherein the second gate electrode has the second thickness.Type: GrantFiled: August 30, 2016Date of Patent: February 27, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-Hoon Son, Jong-Won Kim, Chang-Seok Kang, Young-Woo Park, Jae-Duk Lee, Kyung-Hyun Kim, Byeong-Ju Kim, Phil-Ouk Nam, Kwang-Chul Park, Yeon-Sil Sohn, Jin-I Lee, Won-Bong Jung
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Patent number: 9893077Abstract: A memory device, including a first memory region including a first substrate, a plurality of first semiconductor devices on the first substrate, and a first interlayer insulating layer covering the plurality of first semiconductor devices; and a second memory region including a second substrate on the first interlayer insulating layer and a plurality of second semiconductor devices on the second substrate, the second substrate including a first region in a plurality of grooves in the first interlayer insulating layer and a second region including grains extending from the first region, the second region being on an upper surface of the first interlayer insulating layer.Type: GrantFiled: February 22, 2016Date of Patent: February 13, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Phil Ouk Nam, Yong Hoon Son, Kyung Hyun Kim, Byeong Ju Kim, Kwang Chul Park, Yeon Sil Sohn, Jin I Lee, Jong Heun Lim, Won Bong Jung
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Publication number: 20170098656Abstract: A semiconductor memory device includes insulating patterns and gate patterns alternately stacked on a substrate, a channel structure that intersects the insulating patterns and the gate patterns and connected to the substrate, a charge storage structure between the channel structure and the gate patterns, and a contact structure on the substrate at a side of the insulating patterns and the gate patterns. One of the gate patterns includes a first barrier pattern between a first insulating pattern of the insulating patterns and a second insulating pattern of the insulating patterns adjacent the first insulating pattern in a first direction perpendicular to a main surface of the substrate, the first barrier pattern defining a concave region between a first portion of the first barrier pattern extending along the first insulating pattern and a second portion extending along the second insulating pattern, and a metal pattern in the concave region.Type: ApplicationFiled: August 25, 2016Publication date: April 6, 2017Inventors: Yong-Hoon Son, Kyunghyun KIM, Byeongju KIM, Phil Ouk NAM, Kwangchul PARK, Yeon-Sil SOHN, Jin-I LEE, Wonbong Jung
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Publication number: 20170084532Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a vertical direction with respect to a top surface of the substrate, a plurality of non-metal gate patterns surrounding the channels and being stacked on top of each other and spaced apart from each other along the vertical direction, and a plurality of metal gate patterns stacked on top of each other. The metal gate patterns are spaced apart from each other along the vertical direction. Each of the metal gate patterns surrounds a corresponding one of the non-metal gate patterns.Type: ApplicationFiled: September 21, 2016Publication date: March 23, 2017Inventors: Yong-Hoon SON, Cha-Dong YEO, Han-Mei CHOI, Kyung-Hyun KIM, Phil-Ouk NAM, Kwang-Chui PARK, Yeon-Sil SOHN, Jin-I LEE, Won-Bong JUNG
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Publication number: 20170069637Abstract: A nonvolatile memory device includes a conductive line disposed on a substrate and vertically extended from the substrate, a first channel layer disposed on the substrate and vertically extended from the substrate, wherein the first channel layer is spaced apart from the conductive line, a second channel layer vertically extended from the substrate, wherein the second channel layer is disposed between the first channel layer and the conductive line, a first gate electrode disposed between the conductive line and the second channel layer, wherein the first gate electrode includes a first portion having a first thickness and a second portion having a second thickness that is different from the first thickness, and a second gate electrode disposed between the first channel layer and the second channel layer, wherein the second gate electrode has the second thickness.Type: ApplicationFiled: August 30, 2016Publication date: March 9, 2017Inventors: YONG-HOON SON, JONG-WON KIM, CHANG-SEOK KANG, YOUNG-WOO PARK, JAE-DUK LEE, KYUNG-HYUN KIM, BYEONG-JU KIM, PHIL-OUK NAM, KWANG-CHUL PARK, YEON-SIL SOHN, JIN-I LEE, WON-BONG JUNG
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Publication number: 20170062471Abstract: A semiconductor memory device is disclosed. The device may include a stack including gate electrodes stacked on a substrate in a vertical direction and insulating patterns interposed between the gate electrodes, vertical channels passing through the stack and connected to the substrate, a tunnel insulating layer enclosing each of the vertical channels, charge storing patterns provided between the tunnel insulating layer and the gate electrodes and spaced apart from each other in the vertical direction, blocking insulating patterns provided between the charge storing patterns and the gate electrodes and spaced apart from each other in the vertical direction, and a bit line crossing the stack and connected to the vertical channels. The blocking insulating patterns may have a vertical thickness that is greater than that of the gate electrodes.Type: ApplicationFiled: August 27, 2016Publication date: March 2, 2017Inventors: Yong-Hoon SON, JIN-I LEE, Kyunghyun KIM, Byeongju KIM, Phil Ouk NAM, Kwangchul PARK, Yeon-Sil SOHN, JongHeun LIM, Wonbong Jung
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Publication number: 20170025545Abstract: A semiconductor device includes a polycrystalline semiconductor layer on a substrate, first and second stacks on the polycrystalline semiconductor layer, the first and second stacks extending in a first direction, a separation trench between the first and second stacks and extending in the first direction, the separation trench separating the first and second stacks in a second direction crossing the first direction, and vertical channel structures vertically passing through each of the first and second stacks, wherein the polycrystalline semiconductor layer includes a first grain region and a second grain region in contact with each other, the first and second grain region being adjacent to each other along the second direction, and wherein each of the first and second grain regions includes a plurality of crystal grains, each crystal grain having a longitudinal axis parallel to the second direction.Type: ApplicationFiled: June 8, 2016Publication date: January 26, 2017Inventors: Phil Ouk NAM, Yong-Hoon SON, Kyunghyun KIM, Byeongju KIM, Kwangchul PARK, Yeon-Sil SOHN, Jin-I LEE, JongHeun LIM, Wonbong JUNG
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Publication number: 20160358927Abstract: A memory device, including a first memory region including a first substrate, a plurality of first semiconductor devices on the first substrate, and a first interlayer insulating layer covering the plurality of first semiconductor devices; and a second memory region including a second substrate on the first interlayer insulating layer and a plurality of second semiconductor devices on the second substrate, the second substrate including a first region in a plurality of grooves in the first interlayer insulating layer and a second region including grains extending from the first region, the second region being on an upper surface of the first interlayer insulating layer.Type: ApplicationFiled: February 22, 2016Publication date: December 8, 2016Inventors: Phil Ouk NAM, Yong Hoon SON, Kyung Hyun KIM, Byeong Ju KIM, Kwang Chul PARK, Yeon Sil SOHN, Jin I LEE, Jong Heun LIM, Won Bong JUNG
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Publication number: 20160343730Abstract: A vertical memory device includes a substrate, a channel on the substrate, extending in a vertical direction with respect to a top surface of the substrate, and including a protrusion at a lower portion of the channel, the protrusion extending in a parallel direction with respect to the top surface of the substrate, a semiconductor pattern connecting the protrusion and the substrate, and gate lines stacked and spaced apart from each other in the vertical direction, the gate lines on the protrusion and the semiconductor pattern and surrounding the channel.Type: ApplicationFiled: May 16, 2016Publication date: November 24, 2016Inventors: Yong-Hoon Son, Kyung-Hyun KIM, Byeong-Ju KIM, Phil-Ouk NAM, Kwang Chul PARK, Yeon-Sil SOHN, Jin-I LEE, Jong-Heun LIM, Won-Bong JUNG, Kohji KANAMORI
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Publication number: 20140011350Abstract: A method of manufacturing a semiconductor device, the method including forming a first gate electrode layer including a semiconductor material on a substrate; performing an annealing process on the first gate electrode layer; performing a dry cleaning process on a surface of the first gate electrode layer after the annealing process; and forming a second gate electrode layer on the first gate electrode layer after the dry cleaning process.Type: ApplicationFiled: July 9, 2013Publication date: January 9, 2014Inventors: CHOONGKEE SEONG, KYUNGHYUN KIM, KIJONG PARK, JIN-I LEE
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Patent number: 8580648Abstract: A capacitor includes an object or a substrate including an insulation layer having an opening, an electrode structure having conductive patterns, a dielectric layer and an upper electrode. The electrode structure may have a first conductive pattern including metal and a second conductive pattern including metal oxide generated from the first conductive pattern. The first conductive pattern may fill the opening and may protrude over the insulation layer. The second conductive pattern may extend from the first conductive pattern. The electrode structure may additionally include a third conductive pattern disposed on the second conductive pattern. The capacitor including the electrode structure may ensure improved structural stability and electrical characteristics.Type: GrantFiled: February 25, 2011Date of Patent: November 12, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Suk-Hun Choi, Kyung-Hyun Kim, Chang-Sup Mun, Sung-Jun Kim, Jin-I Lee
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Publication number: 20110204427Abstract: A capacitor includes an object or a substrate including an insulation layer having an opening, an electrode structure having conductive patterns, a dielectric layer and an upper electrode. The electrode structure may have a first conductive pattern including metal and a second conductive pattern including metal oxide generated from the first conductive pattern. The first conductive pattern may fill the opening and may protrude over the insulation layer. The second conductive pattern may extend from the first conductive pattern. The electrode structure may additionally include a third conductive pattern disposed on the second conductive pattern. The capacitor including the electrode structure may ensure improved structural stability and electrical characteristics.Type: ApplicationFiled: February 25, 2011Publication date: August 25, 2011Inventors: Suk-Hun CHOI, Kyung-Hyun KIM, Chang-Sup MUN, Sung-Jun KIM, Jin-I LEE