Patents by Inventor Jin-Lin Liang
Jin-Lin Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9368387Abstract: A method of forming a shallow trench isolation (STI) structure in a substrate includes forming a pad oxide layer over the substrate. The method includes forming a nitride-containing layer over the pad oxide layer, wherein the nitride-containing layer has a first thickness. The method further includes forming the STI structure extending through the nitride-containing layer, into the substrate. The STI structure has a height above a top surface of the pad oxide layer. The method includes establishing a correlation between the first thickness, the height of the STI structure above the top surface of the pad oxide layer, and an offset between the first thickness and the height of the STI structure above the top surface of the pad oxide layer. The method includes calculating the height of the STI structure above the pad oxide layer based on the correlation, and selectively removing a determined thickness of the STI structure.Type: GrantFiled: September 18, 2015Date of Patent: June 14, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tai-Yung Yu, Hui Mei Jao, Jin-Lin Liang, Chien-Hua Li, Cheng-Long Tao, Shian Wei Mao, Chien-Chang Fang
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Publication number: 20160005669Abstract: A method of forming a shallow trench isolation (STI) structure in a substrate includes forming a pad oxide layer over the substrate. The method includes forming a nitride-containing layer over the pad oxide layer, wherein the nitride-containing layer has a first thickness. The method further includes forming the STI structure extending through the nitride-containing layer, into the substrate. The STI structure has a height above a top surface of the pad oxide layer. The method includes establishing a correlation between the first thickness, the height of the STI structure above the top surface of the pad oxide layer, and an offset between the first thickness and the height of the STI structure above the top surface of the pad oxide layer. The method includes calculating the height of the STI structure above the pad oxide layer based on the correlation, and selectively removing a determined thickness of the STI structure.Type: ApplicationFiled: September 18, 2015Publication date: January 7, 2016Inventors: Tai-Yung YU, Hui Mei JAO, Jin-Lin LIANG, Chien-Hua LI, Cheng-Long TAO, Shian Wei MAO, Chien-Chang FANG
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Patent number: 8696930Abstract: An etchant for removing a porous low-k dielectric layer on a semiconductor substrate includes a hydrofluoric acid-based solvent, a dilating additive for dilating the pores in the porous low-k dielectric, and a passivating additive that forms a passivation layer at the interface between the low-k dielectric layer and the semiconductor substrate.Type: GrantFiled: November 23, 2010Date of Patent: April 15, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-Yung Yu, Yu-Sheng Su, Li-Te Hsu, Jin-Lin Liang, Pin-Chia Su
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Publication number: 20110223767Abstract: A method of recycling a control wafer having a low-k dielectric layer deposited thereon involves etching a portion of the low-k dielectric layer using a plasma resulting in a residual film of the low-k dielectric layer and byproduct particulates of carbon on the substrate. The residual dielectric film is removed by wet etching with a low polarization organic solvent that includes HF and a surfactant.Type: ApplicationFiled: May 24, 2011Publication date: September 15, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jin-Lin Liang, Yu-Sheng Su, Tai-Yung Yu, Perre Kao, Pin Chia Su, Li Te Hsu
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Patent number: 7910014Abstract: A chemical processing bath and system used in semiconductor manufacturing utilizes a dynamic spiking model that essentially constantly monitors chemical concentration in the processing bath and adds fresh chemical on a regular basis to maintain chemical concentrations at desirable levels. Etch rates and etch selectivities are maintained at desirable levels and contamination from undesirable precipitation is avoided. The system and method automatically compare concentration levels to a plurality of control limits associated with various technologies and identify the technology or technologies that may undergo processing.Type: GrantFiled: December 21, 2007Date of Patent: March 22, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-Yung Yu, Yu-Sheng Su, Li Te Hsu, Jin Lin Liang, Shih Cheng Yeh, Pin Chia Su
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Publication number: 20110062375Abstract: An etchant for removing a porous low-k dielectric layer on a semiconductor substrate includes a hydrofluoric acid-based solvent, a dilating additive for dilating the pores in the porous low-k dielectric, and a passivating additive that forms a passivation layer at the interface between the low-k dielectric layer and the semiconductor substrate.Type: ApplicationFiled: November 23, 2010Publication date: March 17, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tai-Yung Yu, Yu-Sheng Su, Li-Te Hsu, Jin-Lin Liang, Pin-Chia Su
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Publication number: 20110014726Abstract: A method for forming a shallow trench isolation (STI) structure with a predetermined target height is provided. A substrate having a pad oxide layer formed on the substrate is provided. A nitride-containing layer with a thickness is formed on the pad oxide. A STI structure is formed and extends through the nitride-containing layer, the pad oxide layer, into the substrate. The thickness of the nitride-containing layer is measured to calculate the height of STI structure according to a correlation between the thickness of the nitride-containing layer and the height of STI structure. A thickness of the top portion STI structure to be removed is determined according to the difference between the height of the STI structure and the predetermined target height and is removed in a first etching process. The nitride-containing layer is removed without etching the STI structure or the pad oxide layer in a second etching process.Type: ApplicationFiled: July 19, 2010Publication date: January 20, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tai-Yung YU, Hue Mei JAO, Jin-Lin LIANG, Chien-Hua LI, Cheng-Long TAO, Shian Wei MAO, Chien-Chang FANG
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Patent number: 7851374Abstract: By exposing a process control wafer having a porous low-k-dielectric layer thereon in an HF-based low-k dielectric etching solvent comprising a dilating additive and a passivating additive, the pores in the low-k dielectric layer are dilated some of which connect with one another to form one or more continuous channels extending through the thickness of the dielectric layer and allowing the HF-based solvent to reach down to the substrate. Then the passivating additive component of the HF-based etching solvent forms a passivation layer at the dielectric layer and the substrate interface that protects substrate from the HF-based etchant.Type: GrantFiled: October 31, 2007Date of Patent: December 14, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-Yung Yu, Yu-Sheng Su, Li-Te Hsu, Jin-Lin Liang, Pin-Chia Su
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Publication number: 20090233447Abstract: A method of recycling a control wafer having a dielectric layer deposited thereon involves removing most of the dielectric layer by plasma etching leaving a residual film of the dielectric and then removing the residual dielectric film by a wet etching process. The combination of the dry and wet etching provides effective removal of the dielectric material without damaging the wafer substrate and any residual wet etching byproduct particulate remaining on the wafer substrate is then removed by APM cleaning and scrubbing.Type: ApplicationFiled: March 11, 2008Publication date: September 17, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jin-Lin Liang, Yu-Sheng Su, Tai-Yung Yu, Perre Kao, Pin-Chia Su, Li Te Hsu
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Publication number: 20090111269Abstract: By exposing a process control wafer having a porous low-k-dielectric layer thereon in an HF-based low-k dielectric etching solvent comprising a dilating additive and a passivating additive, the pores in the low-k dielectric layer are dilated some of which connect with one another to form one or more continuous channels extending through the thickness of the dielectric layer and allowing the HF-based solvent to reach down to the substrate. Then the passivating additive component of the HF-based etching solvent forms a passivation layer at the dielectric layer and the substrate interface that protects substrate from the HF-based etchant.Type: ApplicationFiled: October 31, 2007Publication date: April 30, 2009Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-Yung Yu, Yu-Sheng Su, Li-Te Hsu, Jin-Lin Liang, Pin-Chia Su
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Publication number: 20090087929Abstract: A chemical processing bath and system used in semiconductor manufacturing utilizes a dynamic spiking model that essentially constantly monitors chemical concentration in the processing bath and adds fresh chemical on a regular basis to maintain chemical concentrations at desirable levels. Etch rates and etch selectivities are maintained at desirable levels and contamination from undesirable precipitation is avoided. The system and method automatically compare concentration levels to a plurality of control limits associated with various technologies and identify the technology or technologies that may undergo processing.Type: ApplicationFiled: December 21, 2007Publication date: April 2, 2009Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-Yung Yu, Yu-Sheng Su, Li Te Hsu, Jin Lin Liang, Shih Cheng Yeh, Pin Chia Su