Abstract: A frame synchronization method includes: temporarily storing input data of at least one source frame in a frame buffer according to an input time sequence; generating an output time sequence according to the input time sequence and a delay time; generating output data of a destination frame according to the input data of the source frame; and outputting the output data of the destination frame according to an output time sequence; wherein an average frame rate of the source frame is substantially the same as that of the destination frame.

Abstract: A video signal processing method applied for a TV system is disclosed. In this method, the received video signal is processed by a video decoding process, and then the decoded video signal is processed by a de-interlacing process. A still or corresponsively still image signal is generated and blended with the de-interlaced video signal to generate a blended signal which is displayed to make sure the OSD information can always be shown at the top layer of the screen of the LCD panel.

Abstract: A DTV system with a LCD TV controller and a DTV backend controller is disclosed. The LCD TV controller is applied to receive a decoded video signal from an analog TV signal source. And the LCD TV controller decodes, scales and executes the image process on the video signal according to the display form of the LCD TV. A DTV backend controller is applied to receive a decoded video signal from a digital TV signal source. After decoding the video signal, the DTV backend controller outputs the video signal to the LCD TV controller. The LCD TV controller decode, scales and executes the image process on the video signal according to the display form of the LCD TV. And the LCD TV controller transmits the video signal back to the DTV backend controller for executing the OSD process on the video signal by the DTV backend controller. The video signal is transmitted to a display panel for displaying a corresponding video image.

Abstract: An image processing system, for processing display data and vertical blanking interval data carried by a composite signal, is disclosed. The image process system includes: a video decoder, for decoding the display data to generate corresponding image data; a VBI decoder, for decoding the VBI data to generate corresponding VBI image data; a converter, for converting the VBI image data into color index data; a transmission interface, for transmitting the decoded image data and color index data; and an image processing module, for receiving the image data and the color index data to deinterlace/scale the image data and converting the color index data back into the original VBI image data, mixing the processed image data and the VBI image data such that data to be displayed can be generated.

Abstract: An analog front-end (AFE) circuit of a digital display is disclosed including: a first circuit to intermittently invert a working clock to generate a control signal and to generate a sampling signal, wherein the sampling signal is corresponding to the working clock; a first analog-to-digital converter (ADC) coupled to the first circuit for converting an analog video signal into a first digital video signal according to the sampling signal; a second analog-to-digital converter coupled to the first circuit for converting the analog video signal into a second digital video signal according to the sampling signal; and a first multiplexer for selectively outputting the first digital video signal or the second digital video signal according to the control signal.

Abstract: An image signal processing method adapted to an AFE device, which respectively generates first and second colors of digital signals according to first and second colors of analog signals. First, the first color of odd and even signals and the second color of odd and even signals are generated according to the first and second colors of analog signals, respectively. In a single channel mode, the first color of odd or even signal serves as the first color of digital signal for output, and the second color of odd or even signal serves as the second color of digital signal for output. In a dual channel mode, the first color of odd signal and second color of even signal are synchronously outputted, and the first color of even signal and second color of odd signal are also synchronously outputted. The first color of odd and even signals are combined to form the first color of digital signal, and the second color of odd and even signals are combined to form the second color of digital signal.

Abstract: The invention relates to an image processing chip and related method. The image processing chip includes a pin for receiving a composite signal; a synchronization signal detecting circuit, coupled to the pin, for extracting a synchronization signal from the composite signal; a clamping circuit, coupled to the pin, for adjusting a voltage level of the composite signal according to the synchronization signal; and an analog to digital converter, coupled to the pin, for generating a video signal by sampling the composite signal.

Abstract: A color conversion apparatus and a method of color conversion are described for converting a first color in a first color space to a second color in a second color space. The color conversion apparatus includes a plurality of lookup tables storing color mappings relating the first color space to the second color space and a converter using the lookup tables to convert the first color to the second color. The first color space is the sRGB color space and the second color space is a device dependent color space, or vice versa. To reduce the table size, tables having little effect on the second color contain groups of input colors mapping to a same output color and are implemented with a memory having the address inputs connected to the upper most significant bits of an incoming color value. A gamma correction circuit is used to calculate the remaining tables.

Abstract: A method of adjusting a sampling condition to generate a sampling clock in an analog to digital converter includes performing an analog to digital conversion on an analog input signal to thereby produce a digital sampled signal having a plurality of samples; calculating a difference value between two adjacent samples in the digital sampled signal; comparing the difference value with a threshold; adding the difference value into a sum of differences value if the difference value is greater than the threshold; and generating the sampling clock for the analog to digital converter according to the sum of differences value.

Abstract: A video processing method includes: reading a video signal including a plurality of first fields and a plurality of second fields, where the number of the first fields is different from the number of the second fields; and processing the plurality of first fields of the video signal and/or the plurality of second fields of the video signal to generate a plurality of first pictures and a plurality of second pictures, where the number of the first pictures is equal to the number of the second pictures.

Abstract: A method and apparatus for converting a source frame signal received at a first frame rate to a destination frame signal output at a second frame rate. By adjusting the number of pixel data in the destination frame signal, the second frame rate is made to be the same as the first frame rate. Adjusting the amount of non-visible porch signals for at least one horizontal line of the destination frame signal prevents overflow and underflow conditions. The number of non-visible porch signals is increased to prevent underflow or decreased to prevent overflow. The number of non-visible porch signals in the last horizontal line is adjusted to comply with some display devices having a maximum time constraint from a last horizontal sync signal to a vertical sync signal in the destination frame signal.

Abstract: An image displaying method for a television includes: selecting a portion of a plurality of display regions of a screen of the television to display a still or animated image when a power-on signal is received; and utilizing all the plurality of display regions to display images corresponding to a television signal after a predetermined time period beginning from when the power-on signal is received. The present invention further discloses an image displaying method for a television, including: selecting a portion of a plurality of display regions of a screen of the television and stopping the displaying of images corresponding to a television signal on the selected display regions when a power-off signal is received; and stopping the displaying of images corresponding to the television signal on all the plurality of display regions after a predetermined time period beginning from when the power-off signal is received.

Abstract: A source frame signal received at a first frame rate is converted to a destination frame signal output at a second frame rate. By adjusting the clock frequency of the clock signal in the destination frame signal, the second frame rate is made to be the same as the first frame rate. Adjusting the destination clock frequency prevents overflow and underflow conditions. The destination clock frequency is decreased to prevent underflow or increased to prevent overflow. The destination clock frequency during the last horizontal line is adjusted to comply with some display devices having a maximum time constraint from a last horizontal sync signal to a vertical sync signal in the destination frame signal.

Abstract: An image processing method for adjusting color data of an image is disclosed. The color space of the image is divided into a plurality of color grids and the method includes: providing a first table recorded a plurality of parameters corresponding to the plurality of color grids, respectively; receiving color data of the target pixel of the image; selecting a parameter from the first table according to the color data of the target pixel; and adjusting the color data of the target pixel according to the selected parameter.

Abstract: A method of adjusting a sampling condition to generate a sampling clock in an analog to digital converter includes performing an analog to digital conversion on an analog input signal to thereby produce a digital sampled signal having a plurality of samples; calculating a difference value between two adjacent samples in the digital sampled signal; comparing the difference value with a threshold; adding the difference value into a sum of differences value if the difference value is greater than the threshold; and generating the sampling clock for the analog to digital converter according to the sum of differences value.

Abstract: A source frame signal received at a first frame rate is converted to a destination frame signal output at a second frame rate. By adjusting the clock frequency of the clock signal in the destination frame signal, the second frame rate is made to be the same as the first frame rate. Adjusting the destination clock frequency prevents overflow and underflow conditions. The destination clock frequency is decreased to prevent underflow or increased to prevent overflow. The destination clock frequency during the last horizontal line is adjusted to comply with some display devices having a maximum time constraint from a last horizontal sync signal to a vertical sync signal in the destination frame signal.

Abstract: An analog front-end (AFE) circuit of a digital display is disclosed including: a first circuit to intermittently invert a working clock to generate a control signal and to generate a sampling signal, wherein the sampling signal is corresponding to the working clock; a first analog-to-digital converter (ADC) coupled to the first circuit for converting an analog video signal into a first digital video signal according to the sampling signal; a second analog-to-digital converter coupled to the first circuit for converting the analog video signal into a second digital video signal according to the sampling signal; and a first multiplexer for selectively outputting the first digital video signal or the second digital video signal according to the control signal.

Abstract: An image processing circuit for processing a video signal includes: a separator for separating the video signal into a brightness signal and a color signal; a first filter coupled to the separator for filtering the color signal; and a second filter coupled to the separator for filtering the brightness signal.

Abstract: A method includes utilizing the look-up table to store a plurality of basic values and a plurality of delta value sets, wherein each of the delta value sets represents a difference between a corresponding basic value and another basic value adjacent to the corresponding basic value; determining a first basic value and a first delta value set according to an input value; and generating an output value according to the first basic value and the first delta value set.

Abstract: A source frame signal received at a first frame rate is converted to a destination frame signal output at a second frame rate. By adjusting the clock frequency of the clock signal in the destination frame signal, the second frame rate is made to be the same as the first frame rate. Adjusting the destination clock frequency prevents overflow and underflow conditions. The destination clock frequency is decreased to prevent underflow or increased to prevent overflow. The destination clock frequency during the last horizontal line is adjusted to comply with some display devices having a maximum time constraint from a last horizontal sync signal to a vertical sync signal in the destination frame signal.