Patents by Inventor Jin-sheng Shyr

Jin-sheng Shyr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6968514
    Abstract: A method for designing a circuit block includes the steps of selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, at least one of said circuit blocks being programmable; collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method; accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk; upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks (FEA); and, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, in compliance with the criteria and modified constraints without changing the selected circuit block and the processing method.
    Type: Grant
    Filed: March 19, 2001
    Date of Patent: November 22, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Laurence H. Cooke, Kumar Venkatramani, Jin-Sheng Shyr
  • Patent number: 6871341
    Abstract: Embodiments of adaptive scheduling of function calls in dynamic reconfiguration logic are generally disclosed herein. In this regard, accordance with but one example embodiment, a method of scheduling function calls in a software program in a dynamically reconfigurable computing system which includes an embedded processor and a finite number of reconfigurable logic partitions which are each programmed by a set of configuration bits dynamically loaded into the system's configuration memory is disclosed.
    Type: Grant
    Filed: March 24, 2000
    Date of Patent: March 22, 2005
    Assignee: Intel Corporation
    Inventor: Jin-sheng Shyr
  • Patent number: 6519674
    Abstract: A configuration bit layout for a reconfigurable chip includes address bits stored along with configuration bits. The blocks of data are loaded onto the reconfigurable chip from an external memory and the address information is decoded to load the configuration bits onto the correct locations in the reconfigurable chip. In this way, configuration data need not be stored sequentially in the external memory. Configurations can be allocated into different slices of the reconfigurable chip as well.
    Type: Grant
    Filed: February 18, 2000
    Date of Patent: February 11, 2003
    Assignee: Chameleon Systems, Inc.
    Inventors: Peter Shing Fai Lam, Dani Dakhil, Jin-sheng Shyr
  • Publication number: 20020073380
    Abstract: A method for designing a circuit block includes the steps of selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, at least one of said circuit blocks being programmable; collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method; accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk; upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks (FEA); and, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, in compliance with the criteria and modified constraints without changing the selected circuit block and the processing method.
    Type: Application
    Filed: March 19, 2001
    Publication date: June 13, 2002
    Applicant: Cadence Design Systems, Inc.
    Inventors: Laurence H. Cooke, Kumar Venkatramani, Jin-Sheng Shyr