Abstract: A camera module includes a lens barrel comprising a lens; an upper housing, coupled to an end of the lens barrel, including an extension portion extending from an external surface of the lens barrel; a lower housing, coupled to the upper housing, configured to have an internal space; and a first substrate, disposed below the lens barrel, comprising an image sensor. A surface of the extension portion is bonded to the lens barrel, and another surface of the extension portion is bonded to the lower housing, and a shape of the first substrate corresponds to a shape of the internal space of the lower housing.

Abstract: A camera module includes a lens barrel comprising a lens; an upper housing, coupled to an end of the lens barrel, including an extension portion extending from an external surface of the lens barrel; a lower housing, coupled to the upper housing, configured to have an internal space; and a first substrate, disposed below the lens barrel, comprising an image sensor. A surface of the extension portion is bonded to the lens barrel, and another surface of the extension portion is bonded to the lower housing, and a shape of the first substrate corresponds to a shape of the internal space of the lower housing.

Abstract: A camera module includes: a lens barrel accommodating a lens; a forwardmost lens disposed closer to an object side than the lens; an energy generation unit configured to supply energy to the forwardmost lens; and an energy transfer member disposed in contact with the forwardmost lens and the energy generation unit, and configured to transfer the supplied energy to the forwardmost lens.

Abstract: Multipath clock and data recovery circuits and multipath I/O devices are described that operate to provide flexible I/O paths for serial data communications. Active unidirectional components such as a clock and data recovery circuit may be used to implement different I/O paths. Bandwidth and signal degradation for high-speed serial data transmission is reduced.

Abstract: Repeaters are described that operate to rapidly transition from low-power standby states to a low frequency signal transmission state. Bandwidth for high-frequency signal transmission is preserved.

Abstract: Repeaters are described that operate to rapidly transition from low-power standby states to a low frequency signal transmission state. Bandwidth for high-frequency signal transmission is preserved.

Abstract: Referenceless clock and data recovery circuits are described that operate to align the clock/data strobe with each data eye to achieve a low bit error rate. The appropriate frequency and phase to be used is determined by an edge counter based frequency error detector and a phase error detector.

Abstract: Referenceless clock and data recovery circuits are described that operate to align the clock/data strobe with each data eye to achieve a low bit error rate. The appropriate frequency and phase to be used is determined by an edge counter based frequency error detector and a phase error detector.

Abstract: Referenceless clock and data recovery circuits are described that operate to align the clock/data strobe with each data eye to achieve a low bit error rate. The appropriate frequency and phase to be used is determined by an edge counter based frequency error detector and a phase error detector.

Abstract: System, methods and apparatus are described that improve link turnaround performance in a differentially driven link. A method performed at a first device coupled to a two-wire serial link includes transmitting from the first device first differentially-encoded data to a second device over the two-wire serial link during a first time period, receiving at the first device second differentially-encoded data from the second device over the two-wire serial link during a second time period, and driving by the first device both wires of the two-wire serial link to a common voltage level during a third time period, the third time period spanning a link turnaround period between the first time period and the second time period. Both wires of the two-wire serial link are driven toward the common voltage level by the second device during the third time period.

Abstract: System, methods and apparatus are described that improve link turnaround performance in a differentially driven link. A method performed at a first device coupled to a two-wire serial link includes transmitting from the first device first differentially-encoded data to a second device over the two-wire serial link during a first time period, receiving at the first device second differentially-encoded data from the second device over the two-wire serial link during a second time period, and driving by the first device both wires of the two-wire serial link to a common voltage level during a third time period, the third time period spanning a link turnaround period between the first time period and the second time period. Both wires of the two-wire serial link are driven toward the common voltage level by the second device during the third time period.

Abstract: Systems and methods for rate detection for SOUNDWIRE extension (SOUNDWIRE-XL) cables are disclosed. In one aspect, software may be used to initiate a capability exchange between a host device and a slave device over a SOUNDWIRE-XL cable. In a second exemplary aspect, resistors may be associated with data lines in the slave device. Designers may encode rate information into the slave device by using different values for the elements. The host device may then sample the data lanes and determine a rate for the slave device.

Abstract: A high-speed signal level detector employs the high gain and high bandwidth of an inverter to perform a comparison. The high-speed signal level detector is capable of achieving the desired high-speed level detection without demanding the substantial power consumption required when using either the averaging technique or a high bandwidth op-amp type comparator.

Abstract: A temperature independent CMOS reference voltage circuit includes a CMOS current mirror circuit containing first and second CMOS transistors of a first polarity. A temperature compensation circuit is coupled to the CMOS current mirror circuit, and contains a first resistor, a second resistor, and third and fourth CMOS transistors of a second polarity. The third and fourth CMOS transistors are configured to operate substantially in a subthreshold region. One of the third and fourth CMOS transistors is diode connected.

Abstract: A high-speed signal level detector employs the high gain and high bandwidth of an inverter to perform a comparison. The high-speed signal level detector is capable of achieving the desired high-speed level detection without demanding the substantial power consumption required when using either the averaging technique or a high bandwidth op-amp type comparator.

Abstract: A temperature independent CMOS reference voltage circuit includes a CMOS current mirror circuit containing first and second CMOS transistors of a first polarity. A temperature compensation circuit is coupled to the CMOS current mirror circuit, and contains a first resistor, a second resistor, and third and fourth CMOS transistors of a second polarity. The third and fourth CMOS transistors are configured to operate substantially in a subthreshold region. One of the third and fourth CMOS transistors is diode connected.