Patents by Inventor Jin-Young Chae
Jin-Young Chae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11972728Abstract: A light emitting display device includes a display panel including a subpixel, and a driver configured to drive the display panel, and in the subpixel, initialization of both ends of an organic light emitting diode is performed simultaneously with writing of a data voltage.Type: GrantFiled: October 30, 2022Date of Patent: April 30, 2024Assignee: LG DISPLAY CO., LTD.Inventors: Jin Woo Lee, Yi Yeon Hwang, Hee Young Chae
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Patent number: 11956998Abstract: A display device includes: a first substrate including a pixel area and a transmissive area; a thin-film transistor on the first substrate; a planarization layer on the thin-film transistor; a first light emitting electrode on the planarization layer; a bank covering a part of the first light emitting electrode; a light emitting layer on the first light emitting electrode; and a second light emitting electrode on the light emitting layer and the bank. The transmissive area includes a transmissive hole penetrating the bank and the planarization layer.Type: GrantFiled: January 4, 2023Date of Patent: April 9, 2024Assignee: Samsung Display Co., Ltd.Inventors: Se Wan Son, Moo Soon Ko, Rae Young Gwak, Jin Seock Ma, Min Jeong Park, Ki Bok Yoo, So La Lee, Jin Goo Jung, Jong Won Chae, Ye Ji Han
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Patent number: 9099557Abstract: A semiconductor device includes a second conductive-type well configured over a substrate, a first conductive-type body region configured over the second conductive-type well, a gate electrode which overlaps a portion of the first conductive-type body region, and a first conductive-type channel extension region formed over the substrate and which overlaps a portion of the gate electrode.Type: GrantFiled: September 26, 2013Date of Patent: August 4, 2015Assignee: MAGNACHIP SEMICONDUCTOR, LTD.Inventors: Jae-Han Cha, Kyung-Ho Lee, Sun-Goo Kim, Hyung-Suk Choi, Ju-Ho Kim, Jin-Young Chae, In-Taek Oh
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Patent number: 8969161Abstract: A semiconductor device includes: an active region configured over a substrate to include a first conductive-type first deep well and second conductive-type second deep well forming a junction therebetween. A gate electrode extends across the junction and over a portion of first conductive-type first deep well and a portion of the second conductive-type second deep well. A second conductive-type source region is in the first conductive-type first deep well at one side of the gate electrode whereas a second conductive-type drain region is in the second conductive-type second deep well on another side of the gate electrode. A first conductive-type impurity region is in the first conductive-type first deep well surrounding the second conductive-type source region and extending toward the junction so as to partially overlap with the gate electrode and/or partially overlap with the second conductive-type source region.Type: GrantFiled: October 3, 2013Date of Patent: March 3, 2015Assignee: Magnachip Semiconductor, Ltd.Inventors: Jae-Han Cha, Kyung-Ho Lee, Sun-Goo Kim, Hyung-Suk Choi, Ju-Ho Kim, Jin-Young Chae, In-Taek Oh
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Patent number: 8853787Abstract: A semiconductor device includes a substrate with one or more active regions and an isolation layer formed to surround an active region and to extend deeper into the substrate than the one or more active regions. The semiconductor further includes a gate electrode, which covers a portion of the active region, and which has one end portion thereof extending over the isolation layer.Type: GrantFiled: November 30, 2012Date of Patent: October 7, 2014Assignee: Magnachip Semiconductor, Ltd.Inventors: Jae-Han Cha, Kyung-Ho Lee, Sun-Goo Kim, Hyung-Suk Choi, Ju-Ho Kim, Jin-Young Chae, In-Taek Oh
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Publication number: 20140151793Abstract: A semiconductor device includes a substrate with one or more active regions and an isolation layer formed to surround an active region and to extend deeper into the substrate than the one or more active regions. The semiconductor further includes a gate electrode, which covers a portion of the active region, and which has one end portion thereof extending over the isolation layer.Type: ApplicationFiled: November 30, 2012Publication date: June 5, 2014Inventors: Jae-Han CHA, Kyung-Ho LEE, Sun-Goo KIM, Hyung-Suk CHOI, Ju-Ho KIM, Jin-Young CHAE, In-Taek OH
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Patent number: 8716796Abstract: A semiconductor device includes a second conductive-type deep well configured above a substrate. The deep well includes an ion implantation region and a diffusion region. A first conductive-type first well is formed in the diffusion region. A gate electrode extends over portions of the ion implantation region and of the diffusion region, and partially overlaps the first well. The ion implantation region has a uniform impurity concentration whereas the impurity concentration of the diffusion region varies from being the highest concentration at the boundary interface between the ion implantation region and the diffusion region to being the lowest at the portion of the diffusion region that is the farthest away from the boundary interface.Type: GrantFiled: August 1, 2013Date of Patent: May 6, 2014Assignee: MagnaChip Semiconductor, Ltd.Inventors: Jae-Han Cha, Kyung-Ho Lee, Sun-Goo Kim, Hyung-Suk Choi, Ju-Ho Kim, Jin-Young Chae, In-Taek Oh
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Patent number: 8692328Abstract: A semiconductor device includes a second conductive-type deep well configured above a substrate. The deep well includes an ion implantation region and a diffusion region. A first conductive-type first well is formed in the diffusion region. A gate electrode extends over portions of the ion implantation region and of the diffusion region, and partially overlaps the first well. The ion implantation region has a uniform impurity concentration whereas the impurity concentration of the diffusion region varies from being the highest concentration at the boundary interface between the ion implantation region and the diffusion region to being the lowest at the portion of the diffusion region that is the farthest away from the boundary interface.Type: GrantFiled: August 1, 2013Date of Patent: April 8, 2014Assignee: MagnaChip Semiconductor, Ltd.Inventors: Jae-Han Cha, Kyung-Ho Lee, Sun-Goo Kim, Hyung-Suk Choi, Ju-Ho Kim, Jin-Young Chae, In-Taek Oh
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Publication number: 20140030862Abstract: A semiconductor device includes: an active region configured over a substrate to include a first conductive-type first deep well and second conductive-type second deep well forming a junction therebetween. A gate electrode extends across the junction and over a portion of first conductive-type first deep well and a portion of the second conductive-type second deep well. A second conductive-type source region is in the first conductive-type first deep well at one side of the gate electrode whereas a second conductive-type drain region is in the second conductive-type second deep well on another side of the gate electrode. A first conductive-type impurity region is in the first conductive-type first deep well surrounding the second conductive-type source region and extending toward the junction so as to partially overlap with the gate electrode and/or partially overlap with the second conductive-type source region.Type: ApplicationFiled: October 3, 2013Publication date: January 30, 2014Applicant: MagnaChip Semiconductor, Ltd.Inventors: Jae-Han CHA, Kyung-Ho LEE, Sun-Goo KIM, Hyung-Suk CHOI, Ju-Ho KIM, Jin-Young CHAE, In-Taek OH
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Publication number: 20140027846Abstract: A semiconductor device includes a second conductive-type well configured over a substrate, a first conductive-type body region configured over the second conductive-type well, a gate electrode which overlaps a portion of the first conductive-type body region, and a first conductive-type channel extension region formed over the substrate and which overlaps a portion of the gate electrode.Type: ApplicationFiled: September 26, 2013Publication date: January 30, 2014Applicant: MAGNACHIP SEMICONDUCTOR, LTD.Inventors: Jae-Han CHA, Kyung-Ho LEE, Sun-Goo KIM, Hyung-Suk CHOI, Ju-Ho KIM, Jin-Young CHAE, In-Taek OH
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Publication number: 20140021541Abstract: A semiconductor device includes a second conductive-type deep well configured above a substrate. The deep well includes an ion implantation region and a diffusion region. A first conductive-type first well is formed in the diffusion region. A gate electrode extends over portions of the ion implantation region and of the diffusion region, and partially overlaps the first well. The ion implantation region has a uniform impurity concentration whereas the impurity concentration of the diffusion region varies from being the highest concentration at the boundary interface between the ion implantation region and the diffusion region to being the lowest at the portion of the diffusion region that is the farthest away from the boundary interface.Type: ApplicationFiled: August 1, 2013Publication date: January 23, 2014Applicant: MagnaChip Semiconductor, Ltd.Inventors: Jae-Han CHA, Kyung-Ho LEE, Sun-Goo KIM, Hyung-Suk CHOI, Ju-Ho KIM, Jin-Young Chae, IN-Taek OH
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Publication number: 20140021542Abstract: A semiconductor device includes a second conductive-type deep well configured above a substrate. The deep well includes an ion implantation region and a diffusion region. A first conductive-type first well is formed in the diffusion region. A gate electrode extends over portions of the ion implantation region and of the diffusion region, and partially overlaps the first well. The ion implantation region has a uniform impurity concentration whereas the impurity concentration of the diffusion region varies from being the highest concentration at the boundary interface between the ion implantation region and the diffusion region to being the lowest at the portion of the diffusion region that is the farthest away from the boundary interface.Type: ApplicationFiled: August 1, 2013Publication date: January 23, 2014Applicant: MagnaChip Semiconductor, Ltd.Inventors: Jae-Han CHA, Kyung-Ho LEE, Sun-Goo KIM, Hyung-Suk CHOI, Ju-Ho KIM, Jin-Young Chae, In-Taek OH
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Patent number: 8575702Abstract: A semiconductor device includes: an active region configured over a substrate to include a first conductive-type first deep well and second conductive-type second deep well forming a junction therebetween. A gate electrode extends across the junction and over a portion of first conductive-type first deep well and a portion of the second conductive-type second deep well. A second conductive-type source region is in the first conductive-type first deep well at one side of the gate electrode whereas a second conductive-type drain region is in the second conductive-type second deep well on another side of the gate electrode. A first conductive-type impurity region is in the first conductive-type first deep well surrounding the second conductive-type source region and extending toward the junction so as to partially overlap with the gate electrode and/or partially overlap with the second conductive-type source region.Type: GrantFiled: September 15, 2010Date of Patent: November 5, 2013Assignee: MagnaChip Semiconductor, Ltd.Inventors: Jae-Han Cha, Kyung-Ho Lee, Sun-Goo Kim, Hyung-Suk Choi, Ju-Ho Kim, Jin-Young Chae, In-Taek Oh
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Patent number: 8552497Abstract: The semiconductor device includes: a first conductive-type first well and a second conductive-type second well configured over a substrate to contact each other; a second conductive-type anti-diffusion region configured in an interface where the first conductive-type first well contacts the second conductive-type second well over the substrate; and a gate electrode configured to simultaneously cross the first conductive-type first well, the second conductive-type anti-diffusion region, and the second conductive-type second well over the substrate.Type: GrantFiled: November 7, 2011Date of Patent: October 8, 2013Assignee: Magnachip Semiconductor, Ltd.Inventors: Jae-Han Cha, Kyung-Ho Lee, Sun-Goo Kim, Hyung-Suk Choi, Ju-Ho Kim, Jin-Young Chae, In-Taek Oh
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Patent number: 8546881Abstract: A semiconductor device includes a second conductive-type well configured over a substrate, a first conductive-type body region configured over the second conductive-type well, a gate electrode which overlaps a portion of the first conductive-type body region, and a first conductive-type channel extension region formed over the substrate and which overlaps a portion of the gate electrode.Type: GrantFiled: September 2, 2010Date of Patent: October 1, 2013Assignee: MagnaChip Semiconductor, Ltd.Inventors: Jae-Han Cha, Kyung-Ho Lee, Sun-Goo Kim, Hyung-Suk Choi, Ju-Ho Kim, Jin-Young Chae, In-Taek Oh
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Patent number: 8546883Abstract: A semiconductor device includes a second conductive-type deep well configured above a substrate. The deep well includes an ion implantation region and a diffusion region. A first conductive-type first well is formed in the diffusion region. A gate electrode extends over portions of the ion implantation region and of the diffusion region, and partially overlaps the first well. The ion implantation region has a uniform impurity concentration whereas the impurity concentration of the diffusion region varies from being the highest concentration at the boundary interface between the ion implantation region and the diffusion region to being the lowest at the portion of the diffusion region that is the farthest away from the boundary interface.Type: GrantFiled: July 13, 2010Date of Patent: October 1, 2013Assignee: MagnaChip Semiconductor, Ltd.Inventors: Jae-Han Cha, Kyung-Ho Lee, Sun-Goo Kim, Hyung-Suk Choi, Ju-Ho Kim, Jin-Young Chae, In-Taek Oh
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Patent number: 8362556Abstract: A semiconductor device includes a substrate with one or more active regions and an isolation layer formed to surround an active region and to extend deeper into the substrate than the one or more active regions. The semiconductor further includes a gate electrode, which covers a portion of the active region, and which has one end; portion thereof extending over the isolation layer.Type: GrantFiled: July 13, 2010Date of Patent: January 29, 2013Assignee: Magnachip Semiconductor, Ltd.Inventors: Jae-Han Cha, Kyung-Ho Lee, Sun-Goo Kim, Hyung-Suk Choi, Ju-Ho Kim, Jin-Young Chae, In-Taek Oh
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Publication number: 20120049278Abstract: The semiconductor device includes: a first conductive-type first well and a second conductive-type second well configured over substrate to contact each other; a second conductive-type anti-diffusion region configured in an interface where the first conductive-type first well contacts the second conductive-type second well over the substrate; and a gate electrode configured to simultaneously cross the first conductive-type first well, the second conductive-type anti-diffusion region, and the second conductive-type second well over the substrate.Type: ApplicationFiled: November 7, 2011Publication date: March 1, 2012Inventors: Jae-Han CHA, Kyung-Ho LEE, Sun-Goo KIM, Hyung-Suk CHOI, Ju-Ho KIM, Jin-Young CHAE, In-Taek OH
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Patent number: 8076726Abstract: The semiconductor device includes: a first conductive-type first well and a second conductive-type second well configured over a substrate to contact each other; a second conductive-type anti-diffusion region configured in an interface where the first conductive-type first well contacts the second conductive-type second well over the substrate; and a gate electrode configured to simultaneously cross the first conductive-type first well, the second conductive-type anti-diffusion region, and the second conductive-type second well over the substrate.Type: GrantFiled: July 14, 2010Date of Patent: December 13, 2011Assignee: Magnachip Semiconductor, Ltd.Inventors: Jae-Han Cha, Kyung-Ho Lee, Sun-Goo Kim, Hyung-Suk Choi, Ju-Ho Kim, Jin-Young Chae, In-Taek Oh
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Publication number: 20110133279Abstract: The semiconductor device includes: a first conductive-type first well and a second conductive-type second well configured over a substrate to contact each other; a second conductive-type anti-diffusion region configured in an interface where the first conductive-type first well contacts the second conductive-type second well over the substrate; and a gate electrode configured to simultaneously cross the first conductive-type first well, the second conductive-type anti-diffusion region, and the second conductive-type second well over the substrate.Type: ApplicationFiled: July 14, 2010Publication date: June 9, 2011Inventors: Jae-Han Cha, Kyung-Ho Lee, Sun-Goo Kim, Hyung-Suk Choi, Ju-Ho Kim, Jin-Young Chae, In-Taek Oh