Abstract: Methods of forming a diffusion break are disclosed. The method includes forming a diffusion break after source/drain formation, by removing a gate stack of the dummy gate to a buried insulator of an SOI substrate, creating a first opening; and filling the first opening with a dielectric to form the diffusion break. An IC structure includes the diffusion break in contact with an upper surface of the buried insulator. In an optional embodiment, the method may also include simultaneously forming an isolation in an active gate to an STI in the SOI substrate.

Abstract: A method of forming a shallow trench isolation (STI) in a semiconductor-on-insulator (SOI) substrate, including an etch stop liner, to mitigate punch through in SOI substrates is disclosed. The method may include providing an SOI substrate, forming an STI recess within the SOI substrate, forming a first STI dielectric fill within the STI recess wherein a top surface of the first STI dielectric fill is at a location above a top surface of the base substrate, forming a first etch stop liner on the first STI dielectric fill, and forming a second STI dielectric fill over the first etch stop liner. The first etch stop liner is configured so that portion of a contact opening later formed is positioned over the first etch stop liner such that the etch stop liner prevents punch through into the STI. The method may also include forming a second etch stop liner after forming the STI recess and before forming the first STI dielectric fill.

Abstract: The integrated circuit described herein includes: a first resistor having a first trench in a dielectric layer, the first trench having a first width; a second resistor having a second trench in the dielectric layer, the second trench having a second width not equal to the first width; a trench in a dielectric layer, a first conductive layer having a first TCR and coating at least a portion of the first trench and the second trench; and a second conductive layer having a second TCR and coating at least a portion of the first conductive layer in each of the first trench and the second trench, wherein the second TCR is not equal to the first TCR, and wherein the TCR of the IC is selected based on a dimension of the trench, a thickness of the first conductive layer, and a thickness of the second conductive layer.

Abstract: A method of manufacturing a semiconductor device with an embedded layer, by anisotropically etching a substrate adjacent to an already formed gate structure. A dummy layer is deposited in the previously etched region, and a second spacer is formed next to the first spacer. The dummy layer is removed, and a second anisotropic etch is performed. A semiconductor substrate is then epitaxially grown in the etched out region to form the embedded layer.

Abstract: The integrated circuit described herein includes: a first resistor having a first trench in a dielectric layer, the first trench having a first width; a second resistor having a second trench in the dielectric layer, the second trench having a second width not equal to the first width; a trench in a dielectric layer; a first conductive layer having a first TCR and coating at least a portion of the first trench and the second trench; and a second conductive layer having a second TCR and coating at least a portion of the first conductive layer in each of the first trench and the second trench, wherein the second TCR is not equal to the first TCR, and wherein the TCR of the IC is selected based on a dimension of the trench, a thickness of the first conductive layer, and a thickness of the second conductive layer.

Abstract: A method of manufacturing a semiconductor device with an embedded layer, by anisotropically etching a substrate adjacent to an already formed gate structure. A dummy layer is deposited in the previously etched region, and a second spacer is formed next to the first spacer. The dummy layer is removed, and a second anisotropic etch is performed. A semiconductor substrate is then epitaxially grown in the etched out region to form the embedded layer.

Abstract: A FinFET semiconductor device fabrication process includes forming a plurality of FinFET fins upon a semiconductor substrate, forming a first dielectric layer upon the semiconductor substrate so that an upper surface of the first dielectric layer is coplanar with upper surfaces of the FinFET fins, forming a plurality of dummy gates upon the FinFET fins and the first dielectric layer orthogonal to the FinFET fins, revealing the FinFET fins by removing first portions of the first dielectric layer from source-drain regions, removing the dummy gates, and subsequent to the removal of the dummy gates, revealing the FinFET fins by removing second portions of the first dielectric layer from channel regions.

Abstract: A FinFET semiconductor device fabrication process includes forming a plurality of FinFET fins upon a semiconductor substrate, forming a first dielectric layer upon the semiconductor substrate so that an upper surface of the first dielectric layer is coplanar with upper surfaces of the FinFET fins, forming a plurality of dummy gates upon the FinFET fins and the first dielectric layer orthogonal to the FinFET fins, revealing the FinFET fins by removing first portions of the first dielectric layer from source-drain regions, removing the dummy gates, and subsequent to the removal of the dummy gates, revealing the FinFET fins by removing second portions of the first dielectric layer from channel regions.

Abstract: A method of forming overlapping contacts in a semiconductor device includes forming a first contact in a dielectric layer; etching the dielectric layer to form a recess adjacent to the first contact and removing a top portion of the first contact while etching the dielectric layer, wherein a bottom portion of the first contact remains in the dielectric layer after the recess is formed in the dielectric layer; and forming a second contact in the recess adjacent to the bottom portion of the first contact and on top of a top surface of the bottom portion of the first contact.

Abstract: A semiconductor device with overlapping contacts is provided. In one aspect, the semiconductor device includes a dielectric layer; a first contact located in the dielectric layer; and a second contact located in the dielectric layer adjacent to the first contact, wherein a portion of the second contact overlaps a top surface of the first contact.

Abstract: A method of forming overlapping contacts in a semiconductor device includes forming a first contact in a dielectric layer; etching the dielectric layer to form a recess adjacent to the first contact and removing a top portion of the first contact while etching the dielectric layer, wherein a bottom portion of the first contact remains in the dielectric layer after the recess is formed in the dielectric layer; and forming a second contact in the recess adjacent to the bottom portion of the first contact and on top of a top surface of the bottom portion of the first contact.