Abstract: The present invention provides a disk detection method and apparatus. The method includes: collecting a set of N pieces of real-time data that are in a one-to-one correspondence with N input/output I/O-related counters of a disk, where the N I/O-related counters include an I/O response time of the disk and a counter affecting the I/O response time; the I/O response time is a time between delivery of an operation request by an application and reception of a response of the disk to the request; determining, according to the N pieces of real-time data, whether the I/O response time is abnormal; and outputting a detection result if the I/O response time is abnormal, where the detection result is used to represent that the I/O response time is abnormal.

Abstract: The present invention provides a disk detection method and apparatus. The method includes: collecting a set of N pieces of real-time data that are in a one-to-one correspondence with N input/output I/O-related counters of a disk, where the N I/O-related counters include an I/O response time of the disk and a counter affecting the I/O response time; the I/O response time is a time between delivery of an operation request by an application and reception of a response of the disk to the request; determining, according to the N pieces of real-time data, whether the I/O response time is abnormal; and outputting a detection result if the I/O response time is abnormal, where the detection result is used to represent that the I/O response time is abnormal.

Abstract: A message management method is performed at a computing device, the method including: storing received messages into a plurality of cache queues according to priorities of the received messages; extracting messages from the plurality of cache queues, and storing the extracted messages into a uniform cache queue, wherein the uniform cache queue includes multiple entries, each entry corresponding to a respective one of the plurality of cache queues; scheduling the stored messages in the uniform cache queue to a plurality of outputting scheduling queues according to their respective priorities ; and transmitting the stored messages from the scheduling queues to respective terminals by using a transmit channel corresponding to the scheduling queues .

Abstract: Embodiments of this application disclose a resource scheduling method performed at a scheduling server. Virtual machine (VM) information of a to-be-created VM is obtained and common resource information is obtained. A preset resource information private copy is updated according to the common resource information. The resource information private copy includes host machine information corresponding to a preset host machine. Finally, according to the resource information private copy, at least one candidate host machine meeting the VM information is obtained, a target host machine is obtained from the at least one candidate host machine, and the VM is created on the target host machine. In the solution, the resource information private copy can be updated in time before the resource scheduling is performed, which ensures synchronization of the resource information private copy and the common resource information, so that a better resource scheduling result is achieved.

Abstract: A hybrid power converter includes a primary switching circuit, an LC circuit, and a secondary switching circuit. The primary switching circuit includes three or more switching transistors in series that may turn on or off according to a switching cycle to generate a series of voltage pulses at a connecting node between two switching transistors. The LC circuit may be coupled via the to the secondary switching circuits to the connecting node of the primary switching circuit. The LC circuit may receive, from the primary switching circuit, a series of pulses via the secondary switching circuits and may generate an inductor current in the LC circuit. The inductor current may charge a capacitor of the LC circuit to generate an output voltage of the hybrid power converter. The output voltage may have a reverse polarity with respect to an input voltage that may be coupled to the primary switching circuit.

Abstract: A power interface system for reducing power variations includes multiple control circuits configured to control a plurality of switching regulators operating at different frequencies to provide a shared output power to a load. Each control circuit receives a power variation signal resulting from a power variation in the shared output power of the plurality of switching regulators, separates a respective frequency component from multiple frequency components of the power variation signal, and controls, based on the separated respective frequency component, a respective switching regulator of the plurality of switching regulators to source current to, or sink current from, the shared output power until the shared output power reaches a threshold level.

Abstract: A voltage converter circuit comprises a charge pump circuit, a pulse width modulation (PWM) filter stage circuit, and a control circuit. The charge pump circuit includes multiple switching transistors arranged as a switching bridge including a first bridge portion connected to a second bridge portion; a midpoint capacitor connected to a circuit node coupling the first bridge portion and the second bridge portion; and a first flying capacitor coupled to the first bridge portion and the second bridge portion. The PWM filter stage circuit is coupled to the charge pump circuit and a first input/output terminal and includes a first inductor coupled to the first flying capacitor and the second bridge portion of the switching bridge. The control circuit is configured to control activation of switching transistors of the switching bridge to generate a regulated voltage at the first input/output terminal.

Abstract: A hybrid power converter circuit includes a switched-capacitor power converter stage and a pulse-width modulation (PWM) or resonant output circuit coupled to a switching node of the switched-capacitor power converter stage. In particular, the PWM or resonant output circuit can include a transformer having a primary winding and a secondary winding magnetically coupled to each other, and the secondary winding is coupled to the output node of the power converter. The switched-capacitor power converter stage is coupled between the input node of the power converter and the primary winding of the transformer, and includes capacitors and switches configured to connect the capacitors to the input node during a first phase of operation and connect the capacitors to the primary winding of the transformer of the PWM or resonant output circuit during a second phase of operation.

Abstract: A power interface system for reducing power variations includes multiple control circuits configured to control a plurality of switching regulators operating at different frequencies to provide a shared output power to a load. Each control circuit receives a power variation signal resulting from a power variation in the shared output power of the plurality of switching regulators, separates a respective frequency component from multiple frequency components of the power variation signal, and controls, based on the separated respective frequency component, a respective switching regulator of the plurality of switching regulators to source current to, or sink current from, the shared output power until the shared output power reaches a threshold level.

Abstract: A power interface device includes a main switching converter, an auxiliary switching converter, a feedback sense circuit, an error amplifier, a high pass filter, a transient detection circuit, and an auxiliary control circuit. The transient detection circuit is configured to receive the higher frequency component of the transient signal and output an enable signal when the higher frequency component of the transient signal falls outside of an operating window range defined by a first threshold and a second threshold and output a disable signal when the higher frequency component of the transient signal stays within the operating window range. The auxiliary control circuit configured to activate the auxiliary switching converter in accordance with the enable signal and to deactivate the auxiliary switching converter in accordance with the disable signal.

Abstract: A switched capacitor power converter includes multiple switching transistors in a default switching path, and an auxiliary soft-charge bypass circuit which includes one or more auxiliary transistors and an impedance element, and provides an auxiliary circuit path through the auxiliary transistor(s) to charge a plurality of capacitors within the converter circuit when the auxiliary soft-charge bypass circuit is activated and at least one of the switching transistors is deactivated. A corresponding control circuit switches the converter circuit from a soft-charging mode in which the auxiliary soft-charge bypass circuit is activated and a switching transistor is deactivated, to an operational mode in which the auxiliary soft-charge bypass circuit is deactivated, the control circuit periodically switching the one or more auxiliary transistors during the soft-charging mode in place of the deactivated switching transistor(s).

Abstract: A slow-disk detection method is disclosed, the method includes: periodically performing sampling in a detection period; each time sampling is performed, obtaining a first delay of data reading or writing that is performed on a hard disk in current sampling, and a first-delay-related indicator value; determining a first range to which the first-delay-related indicator value belongs; and if the first range is full, calculating a first ratio of the first delay to an average delay in a range; and each time after one detection period ends and before a next detection period starts, if a quantity of all delay-related indicator values fall within all full ranges is greater than or equal to a second threshold, calculating an average value of first ratios; and if the average value of the first ratios is greater than or equal to a third threshold, determining that the hard disk is a slow disk.

Abstract: The present invention provides a disk detection method and apparatus. The method includes: collecting a set of N pieces of real-time data that are in a one-to-one correspondence with N input/output I/O-related counters of a disk, where the N I/O-related counters include an I/O response time of the disk and a counter affecting the I/O response time; the I/O response time is a time between delivery of an operation request by an application and reception of a response of the disk to the request; determining, according to the N pieces of real-time data, whether the I/O response time is abnormal; and outputting a detection result if the I/O response time is abnormal, where the detection result is used to represent that the I/O response time is abnormal.

Abstract: A hybrid power converter circuit includes a switched-capacitor power converter stage and a pulse-width modulation (PWM) or resonant output circuit coupled to a switching node of the switched-capacitor power converter stage. In particular, the PWM or resonant output circuit can include a transformer having a primary winding and a secondary winding magnetically coupled to each other, and the secondary winding is coupled to the output node of the power converter. The switched-capacitor power converter stage is coupled between the input node of the power converter and the primary winding of the transformer, and includes capacitors and switches configured to connect the capacitors to the input node during a first phase of operation and connect the capacitors to the primary winding of the transformer of the PWM or resonant output circuit during a second phase of operation.

Abstract: A power interface device includes a main switching converter, an auxiliary switching converter, and a feedback sense circuit. The main switching converter is coupled to an input terminal and an output terminal and configured to operate at a first switching frequency to source a low frequency current from the input terminal to the output terminal. The auxiliary switching converter is coupled to the input terminal and the output terminal in parallel with the main switching converter and configured to operate at a second and higher switching frequency than the first switching frequency to source a fast transient high frequency current from the input terminal to the output terminal.

Abstract: To reduce in-rush currents into a switched capacitor DC/DC converter and detect voltage and current faults, a converter controller is housed along with a current limit series transistor and fault detection circuitry. The series transistor is controlled to limit the in-rush current to a predetermined maximum level during start-up. If the duration of the current limit level, or the time for Vout to achieve a target voltage, exceeds a first threshold time, a first fault detector in the package shuts off the series transistor. During steady state operation, if the input current reaches the limit for a second threshold time or if Vout extends outside a certain range for the second threshold time, a second fault detector in the package shuts off the series transistor.

Abstract: A power interface device includes a main switching converter, an auxiliary switching converter, and a feedback sense circuit. The main switching converter is coupled to an input terminal and an output terminal and configured to operate at a first switching frequency to source a low frequency current from the input terminal to the output terminal. The auxiliary switching converter is coupled to the input terminal and the output terminal in parallel with the main switching converter and configured to operate at a second and higher switching frequency than the first switching frequency to source a fast transient high frequency current from the input terminal to the output terminal.

Abstract: To reduce in-rush currents into a switched capacitor DC/DC converter and detect voltage and current faults, a converter controller is housed along with a current limit series transistor and fault detection circuitry. The series transistor is controlled to limit the in-rush current to a predetermined maximum level during start-up. If the duration of the current limit level, or the time for Vout to achieve a target voltage, exceeds a first threshold time, a first fault detector in the package shuts off the series transistor. During steady state operation, if the input current reaches the limit for a second threshold time or if Vout extends outside a certain range for the second threshold time, a second fault detector in the package shuts off the series transistor.

Abstract: In a current mode controlled switching power supply, current through the inductor is sensed to determine when to turn off or on the switching transistors. The inductor current has a higher frequency AC component and a lower frequency DC component. The AC current feedback path, sensing the ramping ripple current, is separate from the DC current path, sensing the lower frequency average current. Separating the current sensing paths allows the signal to noise ratio of the AC sense signal to be increased and allows the switching noise to be filtered from the DC sense signal. The gain of the DC sense signal is adjusted so that the DC sense signal has the proper proportion to the AC sense signal. The AC sense signal and the DC sense signal are combined by a summing circuit. The composite sense signal is applied to a PWM comparator to control the duty cycle of the switch.

Abstract: In a current mode controlled switching power supply, current through the inductor is sensed to determine when to turn off or on the switching transistors. The inductor current has a higher frequency AC component and a lower frequency DC component. The AC current feedback path, sensing the ramping ripple current, is separate from the DC current path, sensing the lower frequency average current. Separating the current sensing paths allows the signal to noise ratio of the AC sense signal to be increased and allows the switching noise to be filtered from the DC sense signal. The gain of the DC sense signal is adjusted so that the DC sense signal has the proper proportion to the AC sense signal. The AC sense signal and the DC sense signal are combined by a summing circuit. The composite sense signal is applied to a PWM comparator to control the duty cycle of the switch.