Abstract: A pulse width modulator PWM circuit and a corresponding method are presented. The PWM circuit receives a control signal and a clock signal. The PWM circuit generates an output signal based on the control signal and the clock signal. The output signal has a first or second signal value. The PWM circuit has a delay circuit to generate, by delaying the clock signal by a delay period, a first enable signal for setting the output signal to the first signal value. The PWM circuit has a ramp generator to generate a ramp signal based on the clock signal. The PWM circuit has a comparator to generate, by comparing the control signal with the ramp signal, a second enable signal for setting the output signal to the second signal value. By delaying the clock signal by the delay period, a minimum on-time of the output signal may be reduced.

Abstract: A buck converter device with minimum off-time operation, the device comprising a comparator providing an output signal of a minimum off time, a first amplifier, a p-channel MOSFET whose gate is connected to the output of a first amplifier providing a signal threshold voltage to a positive terminal of a comparator, a second amplifier; and, a second p-channel MOSFET whose gate is connected to the output of a second amplifier providing a signal to a negative terminal of a comparator, and a capacitor element. A capacitor establishes a voltage whose rate of change is proportional to power supply Vdd, establishing a time to charge the capacitor to a threshold voltage proportional to (Vdd?Vref)/Vdd, and establishing a minimum off time on the output of a comparator.

Abstract: A circuit and method for power converter for improved current monitoring, comprising a buck converter comprising a high side switch, a current sensing circuits parallel to the buck converter configured to sense a current through a low side switch, and a positive slope inductor coil estimator sensing circuit parallel to a buck converter configured to estimate a current magnitude.

Abstract: A multi-phase DC-to-DC converter is configured to achieve fast transient response and to optimize efficiency over the load range. Phase shedding changes the active number of phases according to output currents. Each phase of the converter has an inductor configured to optimize the efficiency for a range of load currents in which that phase is used. A converter may have 3 phases, the first used only in sleep mode and has a large inductance with low AC losses, the second used in sync mode at low currents and having a lower inductance with low AC losses, the third phase is used in sync mode at high currents and has small inductance with low DC losses. The number of phases is ?2.

Abstract: A current mirror circuit comprising an input driver connected to a plurality of output driver circuits through a current mirror network. The current mirror network is separated into two parts, wherein the first part comprises the input driver circuit and the second part comprises capacitive loads including a filter capacitor. A switch separates the two parts where an amplifier senses the first part and controls the second part to track the first part when the current mirror circuit is activated. The low source resistance of the output of the amplifier facilitates a fast charging of the capacitance of the second part of the current mirror network dramatically improving signal delay and transition time.

Abstract: A buck converter device with a zero-cross comparator with an adaptive threshold. The buck converter comprises of a control block that controls a first p-channel MOSFET switch, and a second n-channel MOSFET switch. The p-channel MOSFET switch and the n-channel MOSFET switch provide a sense signal utilizing parasitic bipolar junction transistors. The p-channel MOSFET provides a sense current for the pnp parasitic bipolar junction transistor, The n-channel MOSFET provides a sense current for the npn parasitic bipolar junction transistor. The sense current is stored on a capacitor, and establishes an adaptive offset adjustment to a zero-cross comparator.

Abstract: A circuit and method for power converter for improved current monitoring, comprising a buck converter comprising a high side switch, a current sensing circuits parallel to the buck converter configured to sense a current through a low side switch, and a positive slope inductor coil estimator sensing circuit parallel to a buck converter configured to estimate a current magnitude.

Abstract: A time off estimator and an adaptive controller implemented on an integrated circuit to emulate current dependent zero crossing circuitry to permit improved performance of a buck type switching mode power supply. The time off estimator circuit is enhanced by an automatic correction circuit for the timing of a zero crossing where energy to a reference capacitor returns to zero and is turned off awaiting the next cycle where the capacitor is again charged and discharged.

Abstract: A current mirror circuit comprising an input driver connected to a plurality of output driver circuits through a current mirror network. The current mirror network is separated into two parts, wherein the first part comprises the input driver circuit and the second part comprises capacitive loads including a filter capacitor. A switch separates the two parts where an amplifier senses the first part and controls the second part to track the first part when the current mirror circuit is activated. The low source resistance of the output of the amplifier facilitates a fast charging of the capacitance of the second part of the current mirror network dramatically improving signal delay and transition time.

Abstract: A time off estimator and an adaptive controller implemented on an integrated circuit to emulate current dependent zero crossing circuitry to permit improved performance of a buck type switching mode power supply. The time off estimator circuit is enhanced by an automatic correction circuit for the timing of a zero crossing where energy to a reference capacitor returns to zero and is turned off awaiting the next cycle where the capacitor is again charged and discharged.

Abstract: A buck converter device with minimum off-time operation, the device comprising a comparator providing an output signal of a minimum off time, a first amplifier, a p-channel MOSFET whose gate is connected to the output of a first amplifier providing a signal threshold voltage to a positive terminal of a comparator, a second amplifier; and, a second p-channel MOSFET whose gate is connected to the output of a second amplifier providing a signal to a negative terminal of a comparator, and a capacitor element. A capacitor establishes a voltage whose rate of change is proportional to power supply Vdd, establishing a time to charge the capacitor to a threshold voltage proportional to (Vdd-Vref)/Vdd, and establishing a minimum off time on the output of a comparator.

Abstract: A fast startup circuit delivers current to a number of loads, comprising a P-channel current mirror circuit that provides current to an N-channel current mirror circuit that distributes current to a plurality of circuit networks. A first capacitor and a second capacitor are charged to two different voltages when the circuit is disabled and the two voltages are equalized when the circuit is enabled creating an initial operational starting point that has a steady state operating voltage that is the same as that during continuous operations. Thus there is no waiting for the fast startup circuit to start from an off condition and build up exponentially to a steady state operational level.

Abstract: A buck converter device with a zero-cross comparator with an adaptive threshold. The buck converter comprises of a control block that controls a first p-channel MOSFET switch, and a second n-channel MOSFET switch. The p-channel MOSFET switch and the n-channel MOSFET switch provide a sense signal utilizing parasitic bipolar junction transistors. The p-channel MOSFET provides a sense current for the pnp parasitic bipolar junction transistor, The n-channel MOSFET provides a sense current for the npn parasitic bipolar junction transistor. The sense current is stored on a capacitor, and establishes an adaptive offset adjustment to a zero-cross comparator.

Abstract: The present disclosure relates to a high efficiency switched mode power supply (SMPS) having increased efficiency due to loss-less coil current estimation for current control. A circuit in the control unit of SMPS comprises a capacitor and the voltage on the capacitor is an integral of the current flowing into the cap over time and if there are current sources which depend on the input and the output voltage, periodically switched with the same signals as the P and N switches, the voltage on the charged capacitor has the same shape as the current through the coil. The signal gleaned from the capacitor voltage are used the same manner by the control unit as it was with the signals from prior art current sensing.

Abstract: Circuits and related methods for artificial ramp generation for pulse-width modulators (PWM) for current control mode switch mode power supplies (SMPS) are disclosed. The artificial ramp generation is separated from a current sensing part and allows easy trimming of both paths. Artificial ramp is generated as a voltage on a capacitor biased by constant current and placed between a voltage sensing node and an input of a PWM comparator. The circuit disclosed reduces circuit complexity and susceptibility to noise and spikes from the input voltage.

Abstract: A multi-phase DC-to-DC converter is configured to achieve fast transient response and to optimize efficiency over the load range. Phase shedding changes the active number of phases according to output currents. Each phase of the converter has an inductor configured to optimize the efficiency for a range of load currents in which that phase is used. A converter may have 3 phases, the first used only in sleep mode and has a large inductance with low AC losses, the second used in sync mode at low currents and having a lower inductance with low AC losses, the third phase is used in sync mode at high currents and has small inductance with low DC losses. The number of phases is ?2.

Abstract: A time off estimator and an adaptive controller implemented on an integrated circuit to emulate current dependent zero crossing circuitry to permit improved performance of a buck type switching mode power supply. The time off estimator circuit is enhanced by an automatic correction circuit for the timing of a zero crossing where energy to a reference capacitor returns to zero and is turned off awaiting the next cycle where the capacitor is again charged and discharged.

Abstract: The present disclosure relates to a high efficiency switched mode power supply (SMPS) having increased efficiency due to loss-less coil current estimation for current control. A circuit in the control unit of SMPS comprises a capacitor and the voltage on the capacitor is an integral of the current flowing into the cap over time and if there are current sources which depend on the input and the output voltage, periodically switched with the same signals as the P and N switches, the voltage on the charged capacitor has the same shape as the current through the coil. The signal gleaned from the capacitor voltage are used the same manner by the control unit as it was with the signals from prior art current sensing.

Abstract: Circuits and related methods for artificial ramp generation for pulse-width modulators (PWM) for current control mode switch mode power supplies (SMPS).are disclosed. The artificial ramp generation is separated from a current sensing part and allows easy trimming of both paths. Artificial ramp is generated as a voltage on a capacitor biased by constant current and placed between a voltage sensing node and an input of a PWM comparator. The circuit disclosed reduces circuit complexity and susceptibility to noise and spikes from the input voltage.