Patents by Inventor Jing-Cheng Lin

Jing-Cheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230146652
    Abstract: A method of manufacturing a semiconductor device includes following operations. A substrate is received. An electrical conductor is formed over a surface of the substrate. A photo-curable material is selectively dispensed over the surface of the substrate. The photo-curable material is irradiated to form a passivation layer is formed over the surface of the substrate. The passivation layer partially covers an edge of the electrical conductor.
    Type: Application
    Filed: January 13, 2023
    Publication date: May 11, 2023
    Inventors: JING-CHENG LIN, LI-HUI CHENG, PO-HAO TSAI
  • Patent number: 11646220
    Abstract: A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: May 9, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Ming Shih Yeh, Jing-Cheng Lin, Hung-Jui Kuo
  • Publication number: 20230138307
    Abstract: An alignment mechanism of a bonding machine includes a support pedestal, three first alignment members, and three second alignment members. The support pedestal includes a supporting surface having a placement area for supporting a first substrate, and the first and second alignment members are arranged around the placement area. The first alignment members each include a protruding part and a base. The protruding part is used in supporting a second substrate, and protrudes from the base and directed to the placement area. The base is used to position the first substrate. The second alignment members position the second substrate to align the first and second substrates and facilitate the bonding of the first and second substrates.
    Type: Application
    Filed: November 2, 2021
    Publication date: May 4, 2023
    Inventor: JING-CHENG LIN
  • Patent number: 11637086
    Abstract: A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: April 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Szu-Wei Lu, Ying-Da Wang, Li-Chung Kuo, Jing-Cheng Lin
  • Publication number: 20230120393
    Abstract: Disclosed is a powder atomic layer deposition equipment with a quick release function, comprising a vacuum chamber, a shaft sealing device, and a driving unit connected to the shaft sealing device. The vacuum chamber is connected to the shaft sealing device, and an enclosed space is formed between the vacuum chamber and the shaft sealing device. At least one air extraction line is located in the shaft sealing device and fluidly connected to the enclosed space, the air extraction line being used in pumping gas out from the enclosed space to fix the vacuum chamber to the shaft sealing device so that the drive unit rotates the vacuum chamber via the shaft sealing device to facilitate the formation of a uniform thin film on powder surface. When the pumping stops, the vacuum chamber can be quickly released from the shaft sealing device to improve the process efficiency and convenience of use.
    Type: Application
    Filed: October 18, 2021
    Publication date: April 20, 2023
    Inventors: JING-CHENG LIN, JUNG-HUA CHANG, CHIA-CHENG KU
  • Patent number: 11631654
    Abstract: A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: April 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Szu-Wei Lu, Ying-Da Wang, Li-Chung Kuo, Jing-Cheng Lin
  • Publication number: 20230112056
    Abstract: A semiconductor package includes a semiconductor die, a thermal conductive through via and a conductive paste. The thermal conductive through via is electrically insulated from the semiconductor die. The conductive paste is disposed over the semiconductor die, wherein the thermal conductive through via is thermally coupled to the semiconductor die through the conductive paste.
    Type: Application
    Filed: December 14, 2022
    Publication date: April 13, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Szu-Wei Lu
  • Publication number: 20230105086
    Abstract: Methods and apparatus for pre-treating semiconductor wafers before edge trimming to enhance wafer edge quality prior to thinning the semiconductor wafers from an initial thickness, and increasing yield post-thinning of the pre-treated, edge trimmed semiconductor wafers.
    Type: Application
    Filed: December 8, 2022
    Publication date: April 6, 2023
    Inventor: Jing-Cheng Lin
  • Publication number: 20230107519
    Abstract: A method for forming a package structure may comprise applying a die and vias on a carrier having an adhesive layer and forming a molded substrate over the carrier and around the vias, and the ends of the vias and mounts on the die exposed. The vias may be in via chips with one or more dielectric layers separating the vias. The via chips 104 may be formed separately from the carrier. The dielectric layer of the via chips may separate the vias from, and comprise a material different than, the molded substrate. An RDL having RDL contact pads and conductive lines may be formed on the molded substrate. A second structure having at least one die may be mounted on the opposite side of the molded substrate, the die on the second structure in electrical communication with at least one RDL contact pad.
    Type: Application
    Filed: December 12, 2022
    Publication date: April 6, 2023
    Inventor: Jing-Cheng Lin
  • Patent number: 11621205
    Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: April 4, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Wei Chen, Li-Chung Kuo, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, Long Hua Lee, Kuan-Yu Huang
  • Publication number: 20230091273
    Abstract: The present disclosure provides a deposition equipment, which includes a reaction chamber, a carrier, a target material, a magnetic device are at least one shield unit. The carrier and the target material are disposed within the containing space, wherein the carrier is for carrying a substrate, also a surface of the target material faces the carrier and the substrate. The magnetic device is disposed on another surface of the target material, to generate a magnetic field within the containing space through the target material. The shield unit is made electrical conductor and is disposed between a portion of the magnetic device and a portion of the target material, wherein the shield unit is for partially blocking and micro-adjusting the magnetic field generated by the magnetic device within the containing space, such that to improve an evenness of thickness for a thin film formed on the substrate.
    Type: Application
    Filed: November 30, 2022
    Publication date: March 23, 2023
    Inventor: JING-CHENG LIN
  • Patent number: 11610911
    Abstract: Semiconductor devices including vertically-stacked combination memory devices and associated systems and methods are disclosed herein. The vertically-stacked combination memory devices include at least one volatile memory die and at least one non-volatile memory die stacked on top of each other. The corresponding stack may be attached to a controller die that is configured to provide interface for the attached volatile and non-volatile memory dies.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: March 21, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Jing Cheng Lin
  • Patent number: 11605579
    Abstract: A semiconductor device includes a substrate, an electrical conductor and a passivation layer. The substrate includes a first surface. The electric conductor is over the first surface of the substrate. The passivation layer is over the first surface of the substrate. The passivation layer includes a first part and a second part. In some embodiments, the first part is in contact with an edge of the electrical conductor, the second part is connected to the first part and apart from the edge of the electrical conductor, and the first part of the passivation layer has curved surface.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: March 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jing-Cheng Lin, Li-Hui Cheng, Po-Hao Tsai
  • Patent number: 11596973
    Abstract: The present disclosure provides a thin-film-deposition equipment with double-shaft shielding device, which includes a reaction chamber, a carrier and a double-shaft shielding device. The double-shaft shielding device includes a first-connecting arm, a second-connecting arm, a first-shield member, a second-shield member, a first driver and a second driver. The first driver is connected to the first-shield member via the first-connecting arm, and the second driver is connected to the second-shield member via the second-connecting arm, for respectively driving and swinging the two shield members to move in opposite directions via the two connecting arms. Thereby, during a cleaning process of the thin-film-deposition equipment, the two drivers swing the two shield members toward each other into a shielding state for covering the carrier, such that to effectively prevent removed pollutants from polluting the carrier during.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: March 7, 2023
    Assignee: SKY TECH INC.
    Inventors: Jing-Cheng Lin, Yu-Te Shen
  • Patent number: 11598006
    Abstract: The present disclosure is a wafer support, which includes a heating unit, an insulating-and-heat-conducting unit and a conduct portion, wherein the insulating-and-heat-conducting unit is positioned between the conduct portion and the heating unit. During a deposition process, an AC bias is formed on the conduct portion to attract a plasma disposed thereabove. The heating unit includes at least one heating coil, wherein the heating coil heats the wafer supported by the wafer support via the insulating-and-heat-conducting unit and the conduct portion. The insulating-and-heat-conducting unit electrically insulates the heating unit and the conduct portion to prevent the AC flowing in the heating coil and the AC bias on the conduct portion from conducting each other, so the wafer support can generate a stable AC bias and temperature to facilitate forming an evenly-distributed thin film on the wafer supported by the wafer support.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: March 7, 2023
    Assignee: SKY TECH INC.
    Inventors: Jing-Cheng Lin, Chun-Fu Wang
  • Patent number: 11597999
    Abstract: The present disclosure relates to a method and device for decreasing generation of surface oxide of aluminum nitride. In a physical vapor deposition process, the aluminum nitride is deposited on a substrate in a deposition chamber to form an aluminum nitride coated substrate. A cooling chamber and a cooling load lock module respectively perform a first stage cooling and a second stage cooling on the aluminum nitride coated substrate in vacuum environments, so as to prevent the aluminum nitride coated substrate with the high temperature from being exposed in an atmosphere environment to generate the surface oxide. The method and device for decreasing the generation of the surface oxide of the aluminum nitride can further eliminate crystal defects caused by that gallium nitride is deposited on the surface oxide of the aluminum nitride in the next process.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: March 7, 2023
    Assignee: SKY TECH INC.
    Inventors: Jing-Cheng Lin, Yao-Syuan Cheng
  • Publication number: 20230069110
    Abstract: The present disclosure provides a quantum dot particle with passivation layer, which mainly includes a one quantum dot (QD) particle, a first-passivation layer and a second-passivation layer, wherein the first-passivation layer is disposed on a surface of the QD particle, and the second-passivation layer is disposed on a surface of the first-passivation layer. A precursor chosen for forming the first-passivation layer does not cause damage to the QD particle. A precursor of the second-passivation layer includes a composition of trimethylaluminum (TMA) and water, or TMA and ozone, wherein a density of the second-passivation layer is greater than that of the first-passivation layer. The precursor of the second-passivation layer is kept out by the first-passivation layer, such that to prevent the precursor of the second-passivation layer from contacting the QD particle and causing deterioration thereto, and hence to improve a life cycle of the QD particle.
    Type: Application
    Filed: September 2, 2021
    Publication date: March 2, 2023
    Inventors: JING-CHENG LIN, JUNG-HUA CHANG
  • Patent number: 11562941
    Abstract: A semiconductor package includes a semiconductor die, a first thermal conductive pattern and a second thermal conductive pattern. The semiconductor die is encapsulated by an encapsulant. The first thermal conductive pattern is disposed aside the semiconductor die in the encapsulant. The second thermal conductive pattern is disposed over the semiconductor die, wherein the first thermal conductive pattern is thermally coupled to the semiconductor die through the second thermal conductive pattern and electrically insulated from the semiconductor die.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: January 24, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Szu-Wei Lu
  • Publication number: 20220415632
    Abstract: The present disclosure provides a thin-film-deposition equipment with shielding device, which includes a reaction chamber, a carrier and a shielding device. The shielding device includes a first-carry arm, a second-carry arm, a first-shield member, a second-shield member and a driver. The driver interconnects the first-carry arm and the second first-carry arm, for driving and swinging the first-shield member and the second-shield member to move in opposite directions via the first-carry arm and the second first-carry arm. During a cleaning process, the driver swings the shield members toward each other into a shielding state for covering the carrier, such that to prevent polluting the carrier during the process of cleaning the thin-film-deposition equipment.
    Type: Application
    Filed: September 24, 2021
    Publication date: December 29, 2022
    Inventors: Jing-Cheng Lin, Yu-Te Shen
  • Publication number: 20220411917
    Abstract: The present disclosure provides a thin-film-deposition equipment with shielding device, which includes a reaction chamber, a carrier and a shielding device. The shielding device includes a first-shield member, a second-shield member and a driver. The first-shield member has a first-inner-edge surface disposed with a protrusion. The second-shield member has a second-inner-edge surface disposed with a cavity. The driver interconnects and drives the first-shield member and the second-shield member to sway in opposite directions. During a cleaning process, the driver swings the shield members toward each other into a shielding state for covering the carrier, such that to prevent polluting the carrier during the process of cleaning the thin-film-deposition equipment.
    Type: Application
    Filed: October 5, 2021
    Publication date: December 29, 2022
    Inventors: JING-CHENG LIN, YU-TE SHEN