Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

Abstract: A semiconductor device of the present invention comprises: a P type semiconductor substrate, an N-well, a first P+ diffusion region, a second P+ diffusion region, a Schottky diode, a first N+ diffusion region, a second N+ diffusion region, a third P+ diffusion region, a fourth P+ diffusion region, a first insulation layer, a second insulation layer, a first parasitic bipolar junction transistor (BJT), and a second parasitic BJT. The Schottky diode is coupled to an input signal. The first N+ diffusion region and the second N+ diffusion region are coupled to a voltage source, respectively. When a voltage level of the input signal is higher than a voltage level of the voltage source, the Schottky diode conducts charges to make the first parasitic BJT and the second parasitic BJT not conducted.

Abstract: A semiconductor device of the present invention comprises: a P type semiconductor substrate, an N-well, a first P+ diffusion region, a second P+ diffusion region, a Schottky diode, a first N+ diffusion region, a second N+ diffusion region, a third P+ diffusion region, a fourth P+ diffusion region, a first insulation layer, a second insulation layer, a first parasitic bipolar junction transistor (BJT), and a second parasitic BJT. The Schottky diode is coupled to an input signal. The first N+ diffusion region and the second N+ diffusion region are coupled to a voltage source, respectively. When a voltage level of the input signal is higher than a voltage level of the voltage source, the Schottky diode conducts charges to make the first parasitic BJT and the second parasitic BJT not conducted.

Abstract: An electrostatic discharge protection circuit includes: an electrostatic protection device coupled between a first reference voltage terminal and a signal pad for protecting a circuit coupled to the signal pad; a bipolar junction transistor including an emitter terminal coupled to the signal pad, a collector terminal coupled to a second reference voltage terminal, and a base terminal coupled to the first reference voltage terminal, wherein the bipolar junction transistor is a parasitic bipolar junction transistor of the electrostatic protection device; and a clamping circuit coupled to the bipolar junction transistor for clamping a conductivity of the bipolar junction transistor according to a signal received at the signal pad.

Abstract: A device for driving an LCD panel comprises: a gray level voltage generation circuit, for generating gray level voltages, and determining whether the gray level voltages are generated by utilizing a first set of reference voltages or a second set of reference voltages according to a polarity inversion control signal, where the gray level voltage generation circuit determines whether a gray level voltage is generated by utilizing a maximum of the first set of reference voltages or a maximum of the second set of reference voltages, and determines whether another gray level voltage is generated by utilizing a minimum of the first set of reference voltages or a minimum of the second set of reference voltages; and a source driving circuit, for selecting a gray level voltage according to display data or inverted data of the display data to drive a source of a display cell of the LCD panel.

Abstract: A charge recycling system of a liquid crystal display includes a controller and at least one switch module. The controller outputs at least one control signal when driving signals of a gate line and a source line of the liquid crystal display are both disabled, and the switch module couples the source line to a voltage supply of a driving circuit of the liquid crystal display according to the control signal. In this way, charges stored in a liquid crystal unit coupled to the source line are recycled to the voltage supply of the driving circuit, therefore raising the utilization efficiency of charges of the liquid crystal display and lowering the power consumed by the liquid crystal display.

Abstract: An amplifying circuit includes an operational amplifier, a pull-up circuit and a pull-down circuit. The operational amplifier generates a first pull-up signal, a first pull-down signal and an output signal, wherein the phases of the first pull-up signal and the first pull-down signal are out of phase with the output signal. The pull-up circuit includes a first controlling module for outputting a second pull-up signal according to the first pull-up signal, and a first adjusting module for adjusting the output signal according to the second pull-up signal. The pull-down circuit includes a second controlling module for outputting a second pull-down signal according to the first pull-down signal, and a second adjusting module for adjusting the output signal according to the second pull-down signal.

Abstract: An amplifying circuit includes an operational amplifier, a pull-up circuit and a pull-down circuit. The operational amplifier generates a first pull-up signal, a first pull-down signal and an output signal, wherein the phases of the first pull-up signal and the first pull-down signal are out of phase with the output signal. The pull-up circuit includes a first controlling module for outputting a second pull-up signal according to the first pull-up signal, and a first adjusting module for adjusting the output signal according to the second pull-up signal. The pull-down circuit includes a second controlling module for outputting a second pull-down signal according to the first pull-down signal, and a second adjusting module for adjusting the output signal according to the second pull-down signal.

Abstract: The invention relates to a layout method for a transistor with improved ESD robustness. The layout method includes defining a ring region from a first conductive type; defining a first and a second rectangular diffusion regions from a second conductive type, wherein the first and second rectangular diffusion regions are isolated from each other; defining a ring diffusion region of the second conductive type between the first and second rectangular diffusion regions; defining a first gate electrode between the first rectangular diffusion region of the second conductive type and the ring diffusion region of the second conductive region; and defining a second gate electrode between the second rectangular diffusion region of the second conductive type and the ring diffusion region of the second conductive type.