Patents by Inventor Jing Ruei Lu
Jing Ruei Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230340298Abstract: The current disclosure describes carrier tape systems, which include a carrier tape including a plurality of pockets. Each pocket contains a semiconductor device adhered to a bottom surface of the pocket by an adhesive. In some embodiments, the adhesive is a reversible adhesive. Use of the adhesive reduces the likelihood the semiconductor device will be damaged due to movement of the semiconductor device in the pocket during shipment of the carrier tape. Methods of forming a semiconductor device carrier systems and methods of supplying semiconductor devices are also described.Type: ApplicationFiled: June 29, 2023Publication date: October 26, 2023Inventors: Chen-Ming Kuo, Jing Ruei Lu, Pei-Haw Tsao
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Patent number: 11725120Abstract: The current disclosure describes carrier tape systems, which include a carrier tape including a plurality of pockets. Each pocket contains a semiconductor device adhered to a bottom surface of the pocket by an adhesive. In some embodiments, the adhesive is a reversible adhesive. Use of the adhesive reduces the likelihood the semiconductor device will be damaged due to movement of the semiconductor device in the pocket during shipment of the carrier tape. Methods of forming a semiconductor device carrier systems and methods of supplying semiconductor devices are also described.Type: GrantFiled: October 30, 2019Date of Patent: August 15, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Ming Kuo, Jing Ruei Lu, Pei-Haw Tsao
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Patent number: 11417643Abstract: Embodiments relate to packages and methods of forming packages. A package includes a package substrate, a first device die, first electrical connectors, an encapsulant, a redistribution structure, and a second device die. The first device die is attached to a side of the package substrate, and the first electrical connectors are mechanically and electrically coupled to the side of the package substrate. The encapsulant at least laterally encapsulates the first electrical connectors and the first device die. The redistribution structure is on the encapsulant and the first electrical connectors. The redistribution structure is directly coupled to the first electrical connectors. The first device die is disposed between the redistribution structure and the package substrate. The second device die is attached to the redistribution structure by second electrical connectors, and the second electrical connectors are directly coupled to the redistribution structure.Type: GrantFiled: November 5, 2019Date of Patent: August 16, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Chih Liu, Kuan-Lin Ho, Wei-Ting Lin, Chin-Liang Chen, Jing Ruei Lu
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Patent number: 11133285Abstract: The present disclosure, in some embodiments, relates to a method of forming a package. The method includes coupling a first package component to a second package component using a first set of conductive elements. A first polymer-comprising material is formed over the second package component and surrounding the first set of conductive elements. The first polymer-comprising material is cured to solidify the first polymer-comprising material. A part of the first polymer-comprising material is removed to expose an upper surface of the second package component. The second package component is coupled to a third package component using a second set of conductive elements that are formed onto the upper surface of the second package component.Type: GrantFiled: March 21, 2019Date of Patent: September 28, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Tse Chen, Yu-Chih Liu, Hui-Min Huang, Wei-Hung Lin, Jing Ruei Lu, Ming-Da Cheng, Chung-Shi Liu
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Publication number: 20210134635Abstract: The current disclosure describes carrier tape systems, which include a carrier tape including a plurality of pockets. Each pocket contains a semiconductor device adhered to a bottom surface of the pocket by an adhesive. In some embodiments, the adhesive is a reversible adhesive. Use of the adhesive reduces the likelihood the semiconductor device will be damaged due to movement of the semiconductor device in the pocket during shipment of the carrier tape. Methods of forming a semiconductor device carrier systems and methods of supplying semiconductor devices are also described.Type: ApplicationFiled: October 30, 2019Publication date: May 6, 2021Inventors: Chen-Ming Kuo, Jing Ruei Lu, Pei-Haw Tsao
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Publication number: 20200066704Abstract: Embodiments relate to packages and methods of forming packages. A package includes a package substrate, a first device die, first electrical connectors, an encapsulant, a redistribution structure, and a second device die. The first device die is attached to a side of the package substrate, and the first electrical connectors are mechanically and electrically coupled to the side of the package substrate. The encapsulant at least laterally encapsulates the first electrical connectors and the first device die. The redistribution structure is on the encapsulant and the first electrical connectors. The redistribution structure is directly coupled to the first electrical connectors. The first device die is disposed between the redistribution structure and the package substrate. The second device die is attached to the redistribution structure by second electrical connectors, and the second electrical connectors are directly coupled to the redistribution structure.Type: ApplicationFiled: November 5, 2019Publication date: February 27, 2020Inventors: Yu-Chih Liu, Kuan-Lin Ho, Wei-Ting Lin, Chin-Liang Chen, Jing Ruei Lu
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Patent number: 10515941Abstract: Embodiments relate to packages and methods of forming packages. A package includes a package substrate, a first device die, first electrical connectors, an encapsulant, a redistribution structure, and a second device die. The first device die is attached to a side of the package substrate, and the first electrical connectors are mechanically and electrically coupled to the side of the package substrate. The encapsulant at least laterally encapsulates the first electrical connectors and the first device die. The redistribution structure is on the encapsulant and the first electrical connectors. The redistribution structure is directly coupled to the first electrical connectors. The first device die is disposed between the redistribution structure and the package substrate. The second device die is attached to the redistribution structure by second electrical connectors, and the second electrical connectors are directly coupled to the redistribution structure.Type: GrantFiled: December 29, 2017Date of Patent: December 24, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chih Liu, Kuan-Lin Ho, Wei-ting Lin, Chin-Liang Chen, Jing Ruei Lu
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Publication number: 20190221544Abstract: The present disclosure, in some embodiments, relates to a method of forming a package. The method includes coupling a first package component to a second package component using a first set of conductive elements. A first polymer-comprising material is formed over the second package component and surrounding the first set of conductive elements. The first polymer-comprising material is cured to solidify the first polymer-comprising material. A part of the first polymer-comprising material is removed to expose an upper surface of the second package component. The second package component is coupled to a third package component using a second set of conductive elements that are formed onto the upper surface of the second package component.Type: ApplicationFiled: March 21, 2019Publication date: July 18, 2019Inventors: Meng-Tse Chen, Yu-Chih Liu, Hui-Min Huang, Wei-Hung Lin, Jing Ruei Lu, Ming-Da Cheng, Chung-Shi Liu
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Patent number: 10269763Abstract: The present disclosure relates to a package-on-package structure providing mechanical strength and warpage control. In some embodiments, the package-on-package structure includes a first set of conductive elements coupling a first package component to a second package component. A first molding material is arranged on the first package component. The first molding material surrounds the first set of conductive elements and outer sidewalls of the second package component and has a top surface below a top surface of the second package component. The stacked integrated chip structure further includes a second set of conductive elements that couples the second package component to a third package component.Type: GrantFiled: March 17, 2017Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Meng-Tse Chen, Yu-Chih Liu, Hui-Min Huang, Wei-Hung Lin, Jing Ruei Lu, Ming-Da Cheng, Chung-Shi Liu
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Publication number: 20180122791Abstract: Embodiments relate to packages and methods of forming packages. A package includes a package substrate, a first device die, first electrical connectors, an encapsulant, a redistribution structure, and a second device die. The first device die is attached to a side of the package substrate, and the first electrical connectors are mechanically and electrically coupled to the side of the package substrate. The encapsulant at least laterally encapsulates the first electrical connectors and the first device die. The redistribution structure is on the encapsulant and the first electrical connectors. The redistribution structure is directly coupled to the first electrical connectors. The first device die is disposed between the redistribution structure and the package substrate. The second device die is attached to the redistribution structure by second electrical connectors, and the second electrical connectors are directly coupled to the redistribution structure.Type: ApplicationFiled: December 29, 2017Publication date: May 3, 2018Inventors: Yu-Chih Liu, Kuan-Lin Ho, Wei-Ting Lin, Chin-Liang Chen, Jing Ruei Lu
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Patent number: 9887144Abstract: A ring structure for chip packaging comprises a frame portion adaptable to bond to a substrate and at least one corner portion. The frame portion surrounds a semiconductor chip and defines an inside opening, and the inside opening exposes a portion of a surface of the substrate. The at least one corner portion extends from a corner of the frame portion toward the chip, and the corner portion is free of a sharp corner.Type: GrantFiled: September 8, 2011Date of Patent: February 6, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Yi Lin, Yu-Chih Liu, Ming-Chih Yew, Tsung-Shu Lin, Bor-Rung Su, Jing Ruei Lu, Wei-Ting Lin
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Publication number: 20180033775Abstract: A method includes bonding a first device die onto a top surface of a package substrate, and performing an expose molding on the first device die and the package substrate. At least a lower portion of the first device die is molded in a molding material. A top surface of the molding material is level with or higher than a top surface of the first device die. After the expose molding, a second device die is bonded onto a top surface of the first device die. The second device die is electrically coupled to the first device die through through-silicon vias in a semiconductor substrate of the first device die.Type: ApplicationFiled: October 6, 2017Publication date: February 1, 2018Inventors: Yu-Chih Liu, Hai-Ming Chen, Wei-Ting Lin, Jing Ruei Lu, Tsung-Ding Wang
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Patent number: 9859265Abstract: Embodiments relate to packages and methods of forming packages. A package includes a package substrate, a first device die, first electrical connectors, an encapsulant, a redistribution structure, and a second device die. The first device die is attached to a side of the package substrate, and the first electrical connectors are mechanically and electrically coupled to the side of the package substrate. The encapsulant at least laterally encapsulates the first electrical connectors and the first device die. The redistribution structure is on the encapsulant and the first electrical connectors. The redistribution structure is directly coupled to the first electrical connectors. The first device die is disposed between the redistribution structure and the package substrate. The second device die is attached to the redistribution structure by second electrical connectors, and the second electrical connectors are directly coupled to the redistribution structure.Type: GrantFiled: June 6, 2014Date of Patent: January 2, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chih Liu, Kuan-Lin Ho, Wei-Ting Lin, Chin-Liang Chen, Jing Ruei Lu
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Patent number: 9793242Abstract: A method includes bonding a first device die onto a top surface of a package substrate, and performing an expose molding on the first device die and the package substrate. At least a lower portion of the first device die is molded in a molding material. A top surface of the molding material is level with or higher than a top surface of the first device die. After the expose molding, a second device die is bonded onto a top surface of the first device die. The second device die is electrically coupled to the first device die through through-silicon vias in a semiconductor substrate of the first device die.Type: GrantFiled: December 30, 2013Date of Patent: October 17, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chih Liu, Hai-Ming Chen, Wei-Ting Lin, Jing Ruei Lu, Tsung-Ding Wang
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Publication number: 20170194289Abstract: The present disclosure relates to a package-on-package structure providing mechanical strength and warpage control. In some embodiments, the package-on-package structure includes a first set of conductive elements coupling a first package component to a second package component. A first molding material is arranged on the first package component. The first molding material surrounds the first set of conductive elements and outer sidewalls of the second package component and has a top surface below a top surface of the second package component. The stacked integrated chip structure further includes a second set of conductive elements that couples the second package component to a third package component.Type: ApplicationFiled: March 17, 2017Publication date: July 6, 2017Inventors: Meng-Tse Chen, Yu-Chih Liu, Hui-Min Huang, Wei-Hung Lin, Jing Ruei Lu, Ming-Da Cheng, Chung-Shi Liu
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Patent number: 9666556Abstract: An integrated circuit (IC) package includes a first substrate; a second substrate disposed over the first substrate; a plurality of connectors disposed between the first and second substrates such to electrically couple the first and second substrate; a constraint layer disposed over the first and second substrates such that a cavity is formed between the constraint layer and the first substrate; and a molding material disposed within the cavity and extending through the constraint layer. The constraint layer has a top surface and an opposing bottom surface and the molding material extends from the top surface to the bottom surface of the constraint layer.Type: GrantFiled: June 29, 2015Date of Patent: May 30, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chih Liu, Chien-Kuo Chang, Chi-Yang Yu, Jing Ruei Lu, Chih-Hao Lin
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Patent number: 9627355Abstract: A package on package structure providing mechanical strength and warpage control includes a first package component coupled to a second package component by a first set of conductive elements. A first polymer-comprising material is arranged between the first package component and the second package component. The first polymer-comprising material surrounds the first set of conductive elements and the second package component. A third package component is coupled to the second package component by a second set of conductive elements. An underfill is arranged on the second package component and surrounds the second set of conductive elements. The first polymer-comprising material extends past sidewalls of the underfill.Type: GrantFiled: May 2, 2016Date of Patent: April 18, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Meng-Tse Chen, Yu-Chih Liu, Hui-Min Huang, Wei-Hung Lin, Jing Ruei Lu, Ming-Da Cheng, Chung-Shi Liu
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Patent number: 9583474Abstract: A package on packaging structure provides for improved thermal conduction and mechanical strength by the introduction of a sold thermal coupler between the first and second packages. The first package has a first substrate and through vias through the first substrate. A first set of conductive elements is aligned with and coupled to the through vias of the first substrate. A solid thermal coupler is coupled to the first set of conductive elements and to a die of the second package. A second set of conductive elements is coupled to the die and a bottom substrate is coupled to the second set of conductive elements. The thermal coupler may be, e.g., an interposer, a heat spreader, or a thermal conductive layer.Type: GrantFiled: January 8, 2015Date of Patent: February 28, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Yi Lin, Jiun Yi Wu, Jing Ruei Lu, Po-Yao Lin, Ming-Chih Yew
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Publication number: 20160379955Abstract: An integrated circuit (IC) package includes a first substrate; a second substrate disposed over the first substrate; a plurality of connectors disposed between the first and second substrates such to electrically couple the first and second substrate; a constraint layer disposed over the first and second substrates such that a cavity is formed between the constraint layer and the first substrate; and a molding material disposed within the cavity and extending through the constraint layer. The constraint layer has a top surface and an opposing bottom surface and the molding material extends from the top surface to the bottom surface of the constraint layer.Type: ApplicationFiled: June 29, 2015Publication date: December 29, 2016Inventors: Yu-Chih Liu, Chien-Kuo Chang, Chi-Yang Yu, Jing Ruei Lu, Chih-Hao Lin
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Publication number: 20160247782Abstract: A package on package structure providing mechanical strength and warpage control includes a first package component coupled to a second package component by a first set of conductive elements. A first polymer-comprising material is arranged between the first package component and the second package component. The first polymer-comprising material surrounds the first set of conductive elements and the second package component. A third package component is coupled to the second package component by a second set of conductive elements. An underfill is arranged on the second package component and surrounds the second set of conductive elements. The first polymer-comprising material extends past sidewalls of the underfill.Type: ApplicationFiled: May 2, 2016Publication date: August 25, 2016Inventors: Meng-Tse Chen, Yu-Chih Liu, Hui-Min Huang, Wei-Hung Lin, Jing Ruei Lu, Ming-Da Cheng, Chung-Shi Liu