Abstract: A monitor method of computer system is provided, applying within an interrupt service routine. According to the application of interrupt service, when the interrupt controller sends an interrupt signal to the CPU, the CPU executes a corresponding interrupt service routine based on the interrupt signal, in the meantime, the daemon program generates an entrant code. Before the interrupt service routine stops, the daemon program generates an exit code and saves both the entrant code and the exit code in a storage device. It is benefit for solving the problems occurred in the debugging process according to the entrant code and the exit code of the storage device, and speeding up the process of testing and researching steps.

Abstract: A method of computer power state management. When an operating system thereof is idle and the processor thereof transits to a clock-suspended power state (C3/C4 state), an arbitrary bit is asserted to prevent requests from being passed through the Northbridge. When the processor is in the C3/C4 state, if a break event is received, the Southbridge transmits the break event to the Northbridge and changes the processor state from C3/C4 to C0 simultaneously. The break event is subsequently transmitted to the processor when the arbitrary bit is disabled.

Abstract: A ROM emulator is used for emulating an operation of a ROM to be inserted into a ROM socket of a motherboard. The ROM emulator includes a plurality of connectors, one of which is selected to be coupled to a connector of the motherboard for communicating the ROM emulator with the motherboard; a rewritable memory for storing therein BIOS codes in a rewritable manner; and a controller coupled to the plurality of connectors and the rewritable memory for controlling the transmission of the BIOS codes from the rewritable memory to the motherboard via the selected connector in a motherboard-identifiable format.

Abstract: This invention relates to a debug device and method thereof and is applied to detect transmission on a bus in a computer system having a CPU, a north bridge chip and a south bridge chip. The debug device consists of a processing unit, a comparing unit and a recording unit. The processing unit receives a first address signal and a second address signal from the north bridge chip, and correspondingly transmits an index signal and a test data to the north bridge chip. The comparing unit compares the first and the second address signal to generate a comparing signal. And the recording unit records the first and the second address signal and the comparing signal. The north bridge chip connects to the south bridge chip via a bus, and the debug device also connects to the south bridge chip. Therefore the north bridge chip and the debug device transmit to both through the south chip.

Abstract: A system and method of real-time power management for use in computer systems. The system utilization is assessed by a North bridge, and a result is transferred to a South bridge. Thereafter, through transmitting sideband signals to a voltage controller and a frequency controller by sideband pins, the North Bridge provides faster and more efficient power management performance than the system management bus (SMBUS).

Abstract: A system and method for power management in computer systems. System status assessed by a Northbridge, and the result transferred to a Southbridge. A system control table is provided in the Southbridge, whereby power management without software control is provided.

Abstract: The present invention relates to a method for testing a chip, particularly to a method for testing chip configuration settings, essentially installing the chip on a main board after the chip fabrication is finished. The test comprises starting power first of all, a power on self test being performed by the system; loading a BIOS program, wherein the BIOS program includes a configuration test process; testing the configuration settings of the chip by the configuration test process; inputting test data in turn; then enabling registers corresponding to the chip configuration space depending on the test data, for starting the chip operation; obtaining the data, produced by the chip operation, to be compared with an expected result, in order for performing the verification of chip configuration settings at the final stage before the actual chip operation is started, so as to speed the development and modification for the chip.

Abstract: A method of computer power state management. When an operating system thereof is idle and the processor thereof transits to a clock-suspended power state (C3/C4 state), an arbitrary bit is asserted to prevent requests from being passed through the Northbridge. When the processor is in the C3/C4 state, if a break event is received, the Southbridge transmits the break event to the Northbridge and changes the processor state from C3/C4 to C0 simultaneously. The break event is subsequently transmitted to the processor when the arbitrary bit is disabled.

Abstract: A method for dynamically adjusting the data transfer order of the Peripheral Component Interconnect Express (PCI Express) root ports is proposed. The method includes: reading the values of the available storage spaces of the first storage units of the PCI Express root ports and the second storage units of the endpoint devices recorded according to the flow control norm of the PCI Express standard; comparing the values of the available storage spaces of the first and second storage units to find the PCI Express root ports with larger data transfer volume; and updating a port arbitration table to adjust the data transfer order of the PCI Express root ports to make the PCI Express root ports with larger data transfer volume have higher priority for data transfer. Thereby, the flexibility and efficiency of the data transfer of the PCI Express root ports can be improved.

Abstract: An adaptive device for a memory simulator is capable of connecting a transmission interface of a memory simulator to a memory socket of a motherboard, in which the transmission interface is not compatible to the memory socket. The adaptive device includes first and second connectors respectively suitable for connecting with a first read-only memory socket and a second read-only memory socket. If the first connector is connected with the first read-only memory socket, a controller of the adaptive device performs a first access mode to access the system code and passes it to the first read-only memory socket via the first connector. If the second connector is connected with the second read-only memory socket, the controller performs a second access mode to access the system code and passes it to the second read-only memory socket via the second connector for the motherboard to execute it.

Abstract: A memory emulating apparatus and its method are proposed to emulate a read-only memory (ROM) of a motherboard. The motherboard has a first or a second ROM socket. The present invention includes a first and second connectors for connecting with the first and the second ROM socket respectively, a rewritable memory for storing a system code and a controller connected with the first and second connectors and the rewritable memory. If the first connector is connected to the first ROM socket, the controller enters a first access mode to access the system code and passes it to the first ROM socket via the first connector. Otherwise, if the second connector is connected to the second ROM socket, the controller enters a second access mode to access the system code and passes it to the second ROM socket via the second connector for the motherboard to check.

Abstract: A system and method for power management in computer systems. System status assessed by a Northbridge, and the result transferred to a Southbridge. A system control table is provided in the Southbridge, whereby power management without software control is provided.

Abstract: A method for dynamically determining bit configuration for a host bridge. The method first obtains information of peripheral components coupled to the host bridge. Next, the method dynamically determines a bit configuration of a processor system bus connecting to the host bridge according to the obtained information.

Abstract: A system and method of real-time power management for use in computer systems. The system utilization is assessed by a North bridge, and a result is transferred to a South bridge. Thereafter, through transmitting sideband signals to a voltage controller and a frequency controller by sideband pins, the North Bridge provides faster and more efficient power management performance than the system management bus (SMBUS).

Abstract: A control method of synchronizing operation frequencies of a CPU and a system RAM in a power management process. A power management process is initialized by a system interrupt generated by a power management event. After sending the interrupt control signal output from the chipset to the CPU, the CPU enters a system management mode to execute an interrupt service routine. The interrupt service routine irrelevant to the system RAM configuration is executed first. The shadow RAM control register of the chipset is programmed using the BIOS program to enable the BIOS ROM. A distant jump command is programmed to jump into a predetermined memory address of the BIOS ROM storing a system RAM frequency modulation program to execute the system RAM frequency program. Therefore, the operation frequencies of the CPU and the system RAM are consistent during the power management process to eliminate the instability of system caused thereby.

Abstract: The present invention relates to a method for testing a chip, particularly to a method for testing chip configuration settings, essentially installing the chip on a main board after the chip fabrication is finished. The test comprises starting power first of all, a power on self test being performed by the system; loading a BIOS program, wherein the BIOS program includes a configuration test process; testing the configuration settings of the chip by the configuration test process; inputting test data in turn; then enabling registers corresponding to the chip configuration space depending on the test data, for starting the chip operation; obtaining the data, produced by the chip operation, to be compared with an expected result, in order for performing the verification of chip configuration settings at the final stage before the actual chip operation is started, so as to speed the development and modification for the chip.

Abstract: A control method of synchronizing operation frequencies of a CPU and a system RAM in a power management process. A power management process is initialized by a system interrupt generated by a power management event. After sending the interrupt control signal output from the chipset to the CPU, the CPU enters a system management mode to execute an interrupt service routine. The interrupt service routine irrelevant to the system RAM configuration is executed first. The shadow RAM control register of the chipset is programmed using the BIOS program to enable the BIOS ROM. A distant jump command is programmed to jump into a predetermined memory address of the BIOS ROM storing a system RAM frequency modulation program to execute the system RAM frequency program. Therefore, the operation frequencies of the CPU and the system RAM are consistent during the power management process to eliminate the instability of system caused thereby.