Patents by Inventor Jingchun Li

Jingchun Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240094406
    Abstract: The present invention provides a GPS interference source positioning method, apparatus, electronic device, and readable storage medium, which relates to the technical field of wireless communications.
    Type: Application
    Filed: June 13, 2023
    Publication date: March 21, 2024
    Inventors: Zhiyong FENG, Sai HUANG, Jingchun LI, Yiliang CHEN, Ping ZHANG, Shuo CHANG
  • Publication number: 20220136833
    Abstract: The present disclosure discloses a latitude-free construction method for a gravity acceleration vector under a swaying base earth system. Firstly, a target function based on output information of an accelerator in a fixed-length sliding window under a swaying base is constructed; secondly, measurement information in a period of time window is used to construct the target function, and gradient descent optimization is used to obtain a rough value of qiib0; and finally, the rough value of qiib0 and an apparent motion of a gravity acceleration vector of an inertial system are used to construct the gravity acceleration vector under the earth coordinate system. The present disclosure makes a key breakthrough for solving the problem of high precision alignment of a ship with unknown latitude under a swaying base.
    Type: Application
    Filed: April 21, 2021
    Publication date: May 5, 2022
    Inventors: Guochen Wang, Ya Zhang, Zicheng Wang, Hongze Gao, Yanyan Wang, Chao Liu, Jianbo Shao, Jingchun Li
  • Publication number: 20130137235
    Abstract: A MOS transistor (60, 62) is provided. The structure of the transistor (60, 62) includes: a semiconductor substrate (10), a channel area (20, 24), source/drain regions (22, 26), a gate (30, 32), a gate insulating layer (11), a shallow trench isolation region (12), a passive layer (50, 52), and holes (40, 42) formed with a certain distance to the gate insulating layer (11). Wherein both the shapes of the holes (40, 42) and the Young's modulus' difference between the material in the holes (40, 42) and that around the holes (40, 42) contribute to the stress concentration effect, thus the stress in the channel area (20, 24) is enhanced. The structure of the transistor (60, 62) can greatly reduce the stress attenuation during the transmission from stress resource to the sensitive region, and concentrate the stress in the sensitive region. The structure can be involved in large size device, especially.
    Type: Application
    Filed: April 22, 2011
    Publication date: May 30, 2013
    Applicant: University of Electronic Science and Technology of China
    Inventors: Qi Yu, Xiangzhan Wang, Ning Ning, Jingchun Li, Hongdong Yang, Xianwei Ying, Weijie Zhou, Bin Jiang, Yong Wang