Abstract: A patterned vertical alignment (PVA) pixel electrode is disclosed. The PVA pixel electrode includes a first electrode and a second electrode. The first and second electrodes form a pre-tilt angle with respect to a periphery of the pixel. By disposing unequal lengths of indium-tin oxide (ITO) gaps at a periphery of the first and second electrodes, a distance between the first and second electrodes gradually becomes shortened from the center of the pixel outwards. The ITO gaps which are disposed at the periphery of a thin film transistor (TFT)-array substrate and/or a color filter (CF) are adjusted for eliminating a fringe field effect in the present invention, which a transmittance on the pixel regions is improved and an effect of image display quality is enhanced.

Abstract: A patterned vertical alignment (PVA) pixel electrode is disclosed. The PVA pixel electrode includes a first electrode and a second electrode. The first and second electrodes form a pre-tilt angle with respect to a periphery of the pixel. By disposing unequal lengths of indium-tin oxide (ITO) gaps at a periphery of the first and second electrodes, a distance between the first and second electrodes gradually becomes shortened from the center of the pixel outwards. The ITO gaps which are disposed at the periphery of a thin film transistor (TFT)-array substrate and/or a color filter (CF) are adjusted for eliminating a fringe field effect in the present invention, which a transmittance on the pixel regions is improved and an effect of image display quality is enhanced.

Abstract: The present invention provides a display pane comprising a liquid crystal cell and two polarizers disposed at both sides of the liquid crystal cell, wherein one of the polarizers at one side of the liquid crystal cell includes a compensation film, and a first optical path difference R0 of the compensation film is 0.15 to 0.35 times an optical path difference R of the liquid crystal cell. The liquid crystal display pane of the present invention can have a low cost and a wide viewing angle, so as to solve the problems that the contrast of the conventional display panel is reduced, and the dual compensation films have a higher cost.

Abstract: The present invention discloses a method for manufacturing conductive lines with small line-to-line space. The method for manufacturing conductive lines is to coat photoresist on a conductor layer firstly, after exposure and development treatments, then further perform an ashing treatment to completely remove the corresponding part of the photoresist that is corresponding to the exposure area, and then perform an etching step for the conductor layer to form the required conductive lines. The method provided by the present invention can manufacture wire patterns that meet the requirement of small line-to-line space under a condition that the exposure apparatus has limited exposure accuracy.

Abstract: The present invention provides methods for manufacturing a thin film transistor (TFT) array substrate and a display panel.