Abstract: Disclosed are an analog quantity acquisition method and apparatus. An acquisition circuit with a zero flux current transformer is first used to acquire a current signal, where the acquisition circuit with the zero flux current transformer includes the zero flux current transformer, a compensating winding, and a dynamic detection unit, and the compensating winding generates a reverse excitation potential to counteract an excitation current and eliminate impacts of a ratio error and a phase angle error on accuracy. A multi-segment amplification circuit is used to perform segmented amplification on different ranges of the current signal, and full-range current acquisition is achieved by using different amplification circuits. An analog-to-digital converter chip is used to convert an amplified current signal into a digital signal. The acquisition circuit with the zero flux current transformer is used to eliminate the impacts of the ratio error and the phase angle error on the measurement accuracy.

Abstract: A method for forming capacitor holes is provided. By forming a first material layer and a second material layer which are thinner and are different in materials on a supporting layer as an over-etching depth adjusting layer, when etching holes are formed in a hard mask layer and the hard mask layer is over-etched, a certain over-etching depth may be formed in the second material layer, and the etching holes terminate in the first material layer, so that the etching depth of the etching holes can be corrected and adjusted. Accordingly, the etching holes formed after the hard mask layer is over-etched can have the same depth or have a small depth difference. Therefore, time points at which the plurality of capacitors holes formed expose the corresponding connecting pads are substantially the same or differ very little, improving the performance of the DRAM.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure. The method of manufacturing the semiconductor structure includes: providing a base, where contact structures arranged at intervals are formed on a surface of the base; forming, on the base, a stacked structure including alternately stacked a support layer and a sacrificial layer, where the stacked structure covers the contact structure; forming an isolation structure in the stacked structure, where the isolation structure runs through the sacrificial layer and part of the support layer along a direction perpendicular to the base, and is connected to the base through part of a remaining support layer, to divide the base into a first region and a second region; and forming a capacitor structure in the second region, where the capacitor structure is correspondingly connected to the contact structure in the second region.

Abstract: A method for forming capacitor holes is provided. By forming a first material layer and a second material layer which are thinner and are different in materials on a supporting layer as an over-etching depth adjusting layer, when etching holes are formed in a hard mask layer and the hard mask layer is over-etched, a certain over-etching depth may be formed in the second material layer, and the etching holes terminate in the first material layer, so that the etching depth of the etching holes can be corrected and adjusted. Accordingly, the etching holes formed after the hard mask layer is over-etched can have the same depth or have a small depth difference. Therefore, time points at which the plurality of capacitors holes formed expose the corresponding connecting pads are substantially the same or differ very little, improving the performance of the DRAM.