Abstract: The present application provides a reaction device for improving epitaxial growth uniformity, provided with a main inject port on one side and an exhaust port on the other side, wherein a base is provided between the main inject port and the exhaust port; the reaction cavity is provided with first and second inject pipes; the length directions of the first and second inject pipes are perpendicular to a connecting line between the main inject port and the exhaust port; the lengths of the first and second inject pipes are both equal to the radius of the base; the first and second inject pipes are located in a straight line along the length directions; the first and second inject pipes are each provided with a plurality of holes; and the plurality of holes on the first and second inject pipes are located above the wafer placed on the base.

Abstract: The present application discloses a method for manufacturing a metal gate of a PMOS, comprising: step 1, forming a P-type work function metal layer; step 2, depositing an N-type work function metal layer by means of a PVD process, wherein over a bottom surface of a gate trench, the N-type work function metal layer has a hill profile; step 3, forming a first top barrier metal sublayer by means of a conformal growth process, wherein the first top barrier metal sublayer completely fills a sharp corner area of the N-type work function metal layer at a corner of the gate trench; step 4, growing a second top barrier metal sublayer by means of a PVD bombardment process; step 5, forming a third top barrier metal sublayer and a fourth top barrier metal sublayer; and step 6, forming a metal conductive material layer.

Abstract: The present disclosure addresses and solves the current problem of oxygen accumulation in IL after an HKMG stack is formed. A fabrication method is provided for fabricating high-k/metal gate semiconductor device by forming at least one Titanium (Ti) layer between multiple HK layers. A high-k/metal gate semiconductor device including at least one TiO2 layer between multiple HK layers is also provided.

Abstract: The present disclosure addresses and solves the current problem of oxygen accumulation in IL after an HKMG stack is formed. A fabrication method is provided for fabricating high-k/metal gate semiconductor device by forming at least one Titanium (Ti) layer between multiple HK layers. A high-k/metal gate semiconductor device including at least one TiO2 layer between multiple HK layers is also provided.

Abstract: The present invention provides a method for forming a cobalt barrier layer and a metal interconnection process. The method is performed on a surface of a semiconductor device substrate on which metal interconnection lines and an inter-line dielectric layer are formed, and comprises: depositing a dielectric material film on a surface of the inter-line dielectric layer by atomic layer deposition, to densify the surface of the inter-line dielectric layer; removing the deposited dielectric material film, to expose the metal interconnection lines and the densified surface of the inter-line dielectric layer; selectively depositing cobalt on surfaces of the metal interconnection lines to form a cobalt barrier layer. In the present invention, deposition selectivity of cobalt on surfaces of the metal interconnection lines and the inter-line dielectric layer is improved, thus reducing leakage current between metal interconnection lines and improving yield and reliability of the product.

Abstract: The present invention provides a method for forming a cobalt barrier layer and a metal interconnection process. The method is performed on a surface of a semiconductor device substrate on which metal interconnection lines and an inter-line dielectric layer are formed, and comprises: depositing a dielectric material film on a surface of the inter-line dielectric layer by atomic layer deposition, to densify the surface of the inter-line dielectric layer; removing the deposited dielectric material film, to expose the metal interconnection lines and the densified surface of the inter-line dielectric layer, selectively depositing cobalt on surfaces of the metal interconnection lines to form a cobalt barrier layer. In the present invention, deposition selectivity of cobalt on surfaces of the metal interconnection lines and the inter-line dielectric layer is improved, thus reducing leakage current between metal interconnection lines and improving yield and reliability of the product.

Abstract: A method of forming strained source and drain regions in a P-type FinFET structure is disclose. The method comprises depositing an isolation layer on the FinFET structure; applying a lithography and etching process to expose the isolation layer in two areas on opposite sides of the gate over the source/drain region of the FinFET, and etching through the exposed isolation layer to expose the semiconductive material of the source/drain region in the two areas; forming a recess in each of the source/drain region from the exposed semiconductive material; selectively epitaxially growing another semiconductive material in the recesses to increase the source/drain strain; and removing the rest of the isolation layer.

Abstract: A method of forming strained source and drain regions in a P-type FinFET structure is disclose. The method comprises depositing an isolation layer on the FinFET structure; applying a lithography and etching process to expose the isolation layer in two areas on opposite sides of the gate over the source/drain region of the FinFET, and etching through the exposed isolation layer to expose the semiconductive material of the source/drain region in the two areas; forming a recess in each of the source/drain region from the exposed semiconductive material; selectively epitaxially growing another semiconductive material in the recesses to increase the source/drain strain; and removing the rest of the isolation layer.

Abstract: A method of forming a ?-shaped trench is disclosed. The method includes: providing a silicon substrate; and sequentially performing a plasma etching process and a wet etching process on the silicon substrate to form a ?-shaped trench therein. The plasma etching process includes: horizontally etching the silicon substrate using a first plasma etching gas including a nitrogen-containing fluoride; and vertically etching the silicon substrate using a second plasma etching gas including a polymer gas. A method of forming a semiconductor device is also disclosed.

Abstract: The present invention provides a method of forming Cu interconnects. The method comprises depositing an etch stop layer and an insulating layer subsequently; forming vias and trenches in the insulating layer; depositing a diffusion barrier layer and a copper seed layer using PVD; applying electroplating process to form the copper interconnects; depositing a layer of filling materials and reflowing the filling materials to eliminate the uneven surface topography of the copper interconnection layer; and applying annealing and CMP to planarize the top surface of the copper interconnects, and rinsing. According to the method of forming Cu interconnects, the uneven surface topography after electroplating can be reduced, and the surface topography after CMP can be planarized.

Abstract: The present invention provides a method of forming Cu interconnects. The method comprises depositing an etch stop layer and an insulating layer subsequently; forming vias and trenches in the insulating layer; depositing a diffusion barrier layer and a copper seed layer using PVD; applying electroplating process to form the copper interconnects; depositing a layer of filling materials and reflowing the filling materials to eliminate the uneven surface topography of the copper interconnection layer; and applying annealing and CMP to planarize the top surface of the copper interconnects, and rinsing. According to the method of forming Cu interconnects, the uneven surface topography after electroplating can be reduced, and the surface topography after CMP can be planarized.

Abstract: A fabrication method for improving surface planarity after tungsten chemical mechanical polishing (W-CMP) is disclosed. The method forms contact holes and dummy patterns by performing two respective photolithography-and-etching processes to ensure that the dummy patterns have a depth smaller than that of the contact holes. Then the method fills tungsten into the contact holes and dummy patterns and removes the redundant tungsten by a W-CMP process. With such a method, difference of wiring density between areas can be reduced by the dummy patterns, and hence a better surface planarity of the contact hole layer can be achieved. Besides, as the dummy patterns are formed in a pre-metal dielectric layer and their depth is well controlled, tungsten filled in the dummy patterns will not contact with the device area below the pre-metal dielectric layer, and thus will not affect the performance of the device.

Abstract: The present invention disclosed an algorithm of Cu interconnect dummy inserting, including: divide the surface of semiconductor chip into several square windows with an area of A, each of which is non-overlap; perform a logic operation on each square window; and divide the window into two parts: {circle around (1)} the area to-be-inserted; {circle around (2)} the non-inserting area; determine the metal density of the dummy pattern that should be inserted to each square window and the line width; determine the dummy pattern that should be inserted to the windows according to the metal density, line width, the pre-set dummy pattern and the layouting rules. The beneficial effects of the present invention is: avoided the shortcomings of fill density maximization in the rule-based filling method by using reasonable metal density and line width.