Patents by Inventor Jinichi Sakurai

Jinichi Sakurai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4500951
    Abstract: In a plant control system, a transmission channel includes loop transmission lines arranged in duplex. Equivalently connected to this transmission channel are a plurality of one-loop controller stations, a backup station backing up a disabled one of the plural controller stations and a display station for displaying the status of the controller stations and the backup station. Each of the controller stations, backup station and display station includes a built-in microcomputer. Each of these stations includes also a transmission interface circuit and a self-diagnostic circuit. The transmission interface circuit in each station selects one of the transmission lines for data transmission between its own station and the others. The self-diagnostic circuit in each station detects the presence of failure of normal operation of its own station and disconnects the disabled station from the transmission line, so that the other stations may not be adversely affected by the disabled station.
    Type: Grant
    Filed: December 30, 1981
    Date of Patent: February 19, 1985
    Assignee: Hitachi, Ltd.
    Inventors: Norihiko Sugimoto, Nobuhiro Hamada, Ikuro Masuda, Jinichi Sakurai
  • Patent number: 4366478
    Abstract: Disclosed is a signal transmitting and receiving apparatus for transmitting and receiving parallel-by-word data signals, converting the parallel-by-word data signal to serial-by-word data signal, and transmitting the serial-by-word data signal to control units connected in a multi-drop connection configuration or receiving the signals transmitted from the control units.An external control mode and an internal control mode in receiving the parallel-by-word data signal, a simulation mode, and the prevention of competing status between a write timing of the parallel-by-word data to a buffer memory and a read timing of the data for converting it to serial-by-word data are described.
    Type: Grant
    Filed: January 5, 1981
    Date of Patent: December 28, 1982
    Assignee: Hitachi, Ltd.
    Inventors: Ikuro Masuda, Hisayoshi Shiraishi, Seiichiro Ogawa, Shigeo Shiono, Jinichi Sakurai, Takeo Yuminaka