Abstract: Multiple network switches are configured having memory interfaces that transfer segmented frame data to each other via a data path having multiple rings connecting the network switches. The memory interfaces are also configured for transferring the segmented frame data to respective local buffer memories for temporary storage. The data path transfers the data units between the switches according to a prescribed sequence protocol, optimizing memory bandwidth by requiring only one read and one write operation to and from a local buffer memory for each segmented frame data being received and transmitted through the switches.

Abstract: Multiple network switches are configured having memory interfaces that transfer segmented packet data to each other via a unidirectional data bus ring connecting the network switches in a single ring or “daisy chain” arrangement. The memory interfaces are also configured for transferring the segmented packet data to respective local buffer memories for temporary storage. The memory interfaces transfer the data units according to a prescribed sequence, optimizing memory bandwidth by requiring only one read and one write operation to and from the local buffer memory for each segmented packet data being received and transmitted through the switches.

Abstract: Multiple network switch modules have memory interfaces configured for transferring packet data to respective local buffer memories via local memory controllers. The local memory controllers are connected to each other to form a signal memory pool for transfer among each other data units of data frames received from different network switch modules. Each of the controllers are also connected to a corresponding local buffer memory and either write received data units in the corresponding local buffer memory or transfer the received data units to other controllers that, in turn, write the data units in their corresponding local buffer memory. The local memory controllers transfer and write and read the data units according to a prescribed sequence, optimizing memory bandwidth by concurrently executing a prescribed number of successive memory writes or memory reads.