Abstract: A pixel includes: a first transistor including a gate electrode electrically connected to a first node, a second node to which a first power voltage for driving the light emitting element is applied, and a third node electrically connected to the light emitting element; a first emission control transistor having an on-off timing controlled by a first emission control signal; and a second emission control transistor having an on-off timing controlled by a second emission control signal. A time interval exists between a time at which the first emission control signal having a turn-on level is input such that a voltage of the second node is dropped from a bias voltage having a voltage level higher than a voltage level of the first power voltage and a time at which the second emission control signal having a turn-on level is input.

Abstract: A display device includes pixels including a light-emitting element, and an initialization transistor connected between an anode electrode of the light-emitting element and a first initialization power line to which a voltage of initialization power is supplied, and turned on when an initialization scan signal is supplied, and an initialization scan driver which supplies the initialization scan signal. The initial scan driver supplies an i-th (i is a natural number) initial scan signal to overlap an (i?1)-th initial scan signal, and supplies an (i+1)-th initial scan signal so as not to overlap the i-th initial scan signal, and the initialization scan signal is set to a gate-on voltage.

Abstract: A display device includes a display panel which includes first and second pixels disposed in one pixel row, a first gate line connected to the first pixel, a second gate line connected to the second pixel, a first data line connected to the first pixel, and a second data line connected to the second pixel, a gate driver which provides a first gate signal and a second gate signal to the first gate line and the second gate line, respectively, and a data driver disposed adjacent to a first side of the display panel, where the data driver provides a data signal to the first data line. The first data line and the second data line are connected to each other at a second side of the display panel opposite to the first side of the display panel.

Abstract: Disclosed is a display device including a display panel including a pixel, a scan driver, and a driving controller that controls driving of the scan driver. The scan driver provides the pixel with a first mode scan signal having a first active period and a second active period in a first mode and provides the pixel with a second mode scan signal having a compensation active period in a second mode. The driving controller determines whether an operating frequency of the display device corresponds to one of predetermined compensation frequencies in a variable frequency mode, and operates the scan driver in the first mode or the second mode depending on a determination result of the determining.

Abstract: A display apparatus includes a display panel, a gate driver, a data driver and an emission driver. The display panel includes a pixel. The gate driver is configured to output a gate signal to the pixel. The data driver is configured to output a data voltage to the pixel. The emission driver is configured to output an emission signal to the pixel. The pixel includes a light emitting element, a driving switching element configured to apply a driving current to the light emitting element and a bias switching element configured to apply a bias voltage to the driving switching element. The display apparatus increases a level of the bias voltage when a duration of a light emission time of the pixel is increased.

Abstract: A display device includes a display panel, a gate driver, and a driving controller. The display panel includes a pixel. The gate driver applies an anode initialization signal to the pixel. The driving controller receives a horizontal synchronization signal, receives input image data at a variable frame frequency, and controls the gate driver. A frame period for the display panel includes a scan period and one or more hold periods, the driving controller generates a count value by counting a number of pulses of the horizontal synchronization signal, and determines a current frame period as the hold period when the count value exceeds a reference value, and a time length of the anode initialization signal in each of the one or more hold periods is longer than a time length of the anode initialization signal in the scan period.

Abstract: A display device includes: a display panel and a panel driver for driving the display panel during a plurality of driving frames whose frequencies are varied. Among the driving frames, a first driving frame having a first frequency includes a first write period, and a second driving frame having a second frequency lower than the first frequency includes a second write period and a variable blank period. The panel driver includes a data driver and a driving controller. Each of the first and second write periods includes N horizontal periods (N is an integer number equal to or greater than 1), each of the N horizontal periods has a first duration, and each of the first and second write periods has a second duration corresponding to N times of the first duration. The driving controller applies a training synchronizing signal to the data driver during the variable blank period.

Abstract: A pixel connected to a first scan line includes a light-emitting element including an anode and a cathode, a first transistor including a first electrode, a second electrode, and a gate electrode connected to a first node, a first capacitor connected between the first node and a second node, a second transistor connected between the second electrode of the first transistor and the first node including a gate electrode connected to the first scan line, a third transistor including a first electrode, a second electrode connected to the second node, and a gate electrode connected to the first scan line, and a fourth transistor including a first electrode connected to a first driving voltage line, a second electrode connected to the first electrode of the first transistor, and a gate electrode connected to the first scan line.

Abstract: A display device is disclosed that includes a pixel. The pixel includes a first transistor connected between a second node and a third node and including a gate electrode connected to a first node. A first capacitor is formed between the first node and a fourth node. A second capacitor is formed between the fourth node and a first power line. A second transistor is connected between a data line and the fourth node. An eighth transistor is connected between the first power line and the second node. A ninth transistor is connected between the second node and a bias power line. A sixth transistor is connected between the third node and a fifth node. A light emitting element is electrically connected between the fifth node and a second power line. A gate electrode of the eighth transistor and a gate electrode of the sixth transistor are connected to different gate lines.

Abstract: A display device includes: a display panel which displays an image corresponding to each of a plurality of frames, and a source driver which drives the display panel. The plurality of frames includes a first frame operating at a first operating frequency, and a second frame operating at a frequency higher than the first operating frequency. The first frame includes a write cycle section, a hold cycle section, and a blank section including a standby section. The source driver operates in a normal driving mode during the write cycle section and the hold cycle section, and operates in a low-power driving mode during the standby section.

Abstract: A pixel includes: a light-emitting element including an anode and a cathode, a first transistor including a first and a second electrode and a gate electrode connected with a first node, a third transistor connected between the second electrode of the first transistor and the first node and including a gate electrode connected with a first scan line, a sixth transistor connected between the second electrode of the first transistor and the anode and including a gate electrode connected with a first emission line, and a seventh transistor connected between the anode and an initialization voltage line and including a gate electrode connected with a second scan line. During an initialization period, the third, sixth, and seventh transistors are turned on such that an initialization voltage from the initialization voltage line is transferred to the gate electrode of the first transistor.

Abstract: A pixel includes: a light emitting element; a first transistor including a gate electrode electrically connected to a first node, a second node to which a first power voltage for driving the light emitting element is to be applied, and a third node electrically connected to the light emitting element; and a bias control transistor configured to be controlled in operating timing thereof by a bias control signal, and configured to switch electrical connection between the second node and a bias power line for transmitting a bias voltage. In one frame period, a voltage level of the bias voltage to be applied to the second node sequentially increases.

Abstract: A pixel includes: a first transistor including a gate electrode electrically connected to a first node, a second node to which a first power voltage for driving the light emitting element is applied, and a third node electrically connected to the light emitting element; a first emission control transistor having an on-off timing controlled by a first emission control signal; and a second emission control transistor having an on-off timing controlled by a second emission control signal. A time interval exists between a time at which the first emission control signal having a turn-on level is input such that a voltage of the second node is dropped from a bias voltage having a voltage level higher than a voltage level of the first power voltage and a time at which the second emission control signal having a turn-on level is input.

Abstract: A display device includes four pixel arrays, a data driver, and a demultiplexer. The data driver is electrically connected to first and second data output lines. The demultiplexer electrically connects first and second data lines to the first data output line and electrically connects third and fourth data lines to the second data output line. The first to fourth pixel arrays are adjacent to the first to fourth data lines, respectively. Each of the first to fourth pixel arrays includes first and second color pixels. The first color pixels in the second pixel array are connected to the second data line, the second color pixels in the second pixel array are connected to the third data line, the second color pixels in the third pixel array are connected to the third data line, and the first color pixels in the third pixel array are connected to the second data line.

Abstract: A pixel connected to a first scan line includes a light-emitting element including an anode and a cathode, a first transistor including a first electrode, a second electrode, and a gate electrode connected to a first node, a first capacitor connected between the first node and a second node, a second transistor connected between the second electrode of the first transistor and the first node including a gate electrode connected to the first scan line, a third transistor including a first electrode, a second electrode connected to the second node, and a gate electrode connected to the first scan line, and a fourth transistor including a first electrode connected to a first driving voltage line, a second electrode connected to the first electrode of the first transistor, and a gate electrode connected to the first scan line.

Abstract: A pixel includes: a first transistor including a gate electrode electrically connected to a first node, a second node to which a first power voltage for driving the light emitting element is applied, and a third node electrically connected to the light emitting element; a first emission control transistor having an on-off timing controlled by a first emission control signal; and a second emission control transistor having an on-off timing controlled by a second emission control signal. A time interval exists between a time at which the first emission control signal having a turn-on level is input such that a voltage of the second node is dropped from a bias voltage having a voltage level higher than a voltage level of the first power voltage and a time at which the second emission control signal having a turn-on level is input.

Abstract: A display panel of a display device is divided into a first display region and a second display region. The second display region includes a boundary region adjacent to the first display region and a non-boundary region opposite to the first display region with respect to the boundary region. The driving controller outputs the voltage control signal, such that the first voltage in a first high voltage level and the second voltage in a first low voltage level are generated when the first display region is driven. The driving controller outputs the voltage control signal, such that the first voltage in a second high voltage level lower than the first high voltage level and the second voltage in a second low voltage level higher than the first low voltage level are generated, when the non-boundary region of the second display region is driven.

Abstract: A display panel of a display device includes: first light emitting elements located in a first row, second light emitting elements located in a second row adjacent to the first row, first pixel circuits located in the first row, and second pixel circuits located in the second row. Each of the first pixel circuits drives a first light emitting element, located in a column the same as a column in which the each of the first pixel circuits is located, among the first light emitting elements. At least one second pixel circuit of the second pixel circuits drives a second light emitting element, located in a column different from a column in which the at least one second pixel circuit is located, among the second light emitting elements.

Abstract: A display system includes a host processor configured to provide frame data using a scan order, and a display device including a display panel including pixels and a display panel driver configured to refresh the pixels according using the frame data and to provide the scan order to the host processor.

Abstract: A display device includes a display panel including a first pixel connected to a first initialization scan line and a first compensation scan line and a second pixel connected to a second initialization scan line and a second compensation scan line, a scan driving circuit which provides a first initialization scan signal to the first initialization scan line and the second initialization scan line in common and provides a first compensation scan signal and a second compensation scan signal to the first compensation scan line and the second compensation scan line, and a driving controller which controls the scan driving circuit. A delay time from a time point at which the first initialization scan signal transitions from an active level to an inactive level to a time point at which the first compensation scan signal transitions from the inactive level to the active level is less than one horizontal period.