Patents by Inventor Jin-Xing Li

Jin-Xing Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220067128
    Abstract: A terminal device security management device and method are involved a terminal device management field. By grading network level, a level of functions being forbidden to be invoked, formed by obtaining a network connected by the terminal device, is sent to the terminal device for managing invoking operations of the functions. The terminal devices in different management domains are managed based on different connected networks for licensing the terminal device to invoke different function sets in different management domains. Work efficiency is improved, and a risk of leaks is reduced. A terminal device and a method of the terminal device are also disclosed. By responding information of a management device, a licensed function set is displayed in a display, or an invoking of the function is forbidden based on an invoking request for avoiding the specified function to be invoked in the management domain. The leak risk is further reduced.
    Type: Application
    Filed: September 3, 2021
    Publication date: March 3, 2022
    Inventors: JIN-XING LI, ZI-REN GUO, FU-NUNG TSO
  • Patent number: 8007914
    Abstract: A two layer LTO backside seal for a wafer. The two layer LTO backside seal includes a low stress LTO layer having a first major side and a second major side, the first major5 side of the low stress LTO layer adjacent to one major side of the wafer. The two layer LTO backside seal further includes a high stress LTO layer having a first major side and second major side, the first major side of the high stress LTO layer adjacent the second major side of the low stress LTO layer.
    Type: Grant
    Filed: September 18, 2003
    Date of Patent: August 30, 2011
    Assignee: Siltronic AG
    Inventors: Jin-Xing Li, Boon-Koon Ow
  • Publication number: 20070065671
    Abstract: A two layer LTO backside seal for a wafer. The two layer LTO backside seal includes a low stress LTO layer having a first major side and a second major side, the first major5 side of the low stress LTO layer adjacent to one major side of the wafer. The two layer LTO backside seal further includes a high stress LTO layer having a first major side and second major side, the first major side of the high stress LTO layer adjacent the second major side of the low stress LTO layer.
    Type: Application
    Filed: September 18, 2003
    Publication date: March 22, 2007
    Inventor: Jin-Xing Li