Abstract: Systems and methods for enabling serial attached Non-Volatile (NV) memory are provided. In some embodiments, a method of operation of a computing system includes: in an NV Random Access Memory module (NVRAM) having a non-volatile device, a volatile memory device with data, a NV Controller unit (NVC), and a serial host interface, the method includes: receiving a request for data on the serial host interface and providing the requested data, from the volatile memory device, on the serial host interface. The method also includes: detecting a disruptive volatile memory event; copying the data of the volatile memory device to the NV device through the serial host interface based on the disruptive volatile memory event; and restoring the data of the volatile memory device from the NV device through the serial host interface. In this way, Dynamic Random-Access Memory (DRAM) level endurance and speed/latency can be provided while making it NV.

Abstract: A single-slot peripheral component interconnect express (PCIe) card with expanded memory is provided. Embodiments described herein use two rigid circuit boards which are oriented perpendicular to each other. The two rigid circuit boards are connected by a flexible cable, which can be sandwiched between the laminates of the rigid boards. The flexible cable further provides high-speed signal connection and high-power connection between the two rigid boards. In addition, the two rigid boards can be secured by two mechanical retainers. This approach enables a PCIe card to have three or more (e.g., four) dual in-line memory modules (DIMMs) while meeting the PCIe standard for single slot primary side height by placing the DIMM sockets horizontally, thus lowering the overall height of the PCIe card.

Abstract: Approaches, techniques, and mechanisms are disclosed for a centralized backup power support system that improves testability of non-volatile dual in-line memory modules (NVDIMM) on Automatic Test Equipment (ATE) testers and in-system tests. An NVDIMM includes both volatile memories and non-volatile memories. According to an embodiment, a compact backup power distribution board is powered with an external power supply with an individual protection circuit. The backup power distribution board has an unlimited energy capacity for any density of NVDIMM and zero charge waiting time. According to an embodiment, instead of using an electric double-layer capacitor (EDLC) to support backup power, a resistor is used instead of an EDLC on each backup power module. There is no charging time when the backup power module does not have EDLC cells, resulting in significant reduction in test time and production cost and increase in production output.

Abstract: Approaches, techniques, and mechanisms are disclosed for a test adapter designed to improve testability of non-volatile dual in-line memory modules (NVDIMM) on automatic test equipment (ATE) testers or in-system boards, which have inadequate power supplies. An NVDIMM includes both volatile memories and non-volatile memories. A test adapter is designed to supply increased power to an NVDIMM. A test adapter is implemented using an interposer or a printed circuit board (PCB) that may be inserted into a socket on an ATE tester or on an end-user system-level board. The interposer or PCB includes a power socket for attaching a power cable to supply the external power supply to the NVDIMM. A power on/off sequence is controlled by an ATE tester to simulate or test a system power on/off sequence. An external input power is always on, but both serial and backup power signals are only on during tests of an NVDIMM.

Abstract: Approaches, techniques, and mechanisms are disclosed for improving the performance of memory controllers for memory devices. A system may have a memory controller that interfaces with a memory device to store or retrieve information. When the system needs to retrieve information from the memory device, the memory controller sends an address and a command to instruct the memory device to read the information stored at the address. The memory device reads the information, and after a specific amount of time, the memory device sends the information to the memory controller. According to an embodiment, “dummy” data is sent first prior to the availability of the data read out of the memory devices, while waiting for the requested data to be accessed, and then the actual data is sent immediately following the dummy data. According to an embodiment, a geometry of a memory device has only one column of memory cells that are used to store information.

Abstract: Approaches, techniques, and mechanisms are disclosed for improving the performance of memory controllers for memory devices. A system may have a memory controller that interfaces with a memory device to store or retrieve information. When the system needs to retrieve information from the memory device, the memory controller sends an address and a command to instruct the memory device to read the information stored at the address. The memory device reads the information, and after a specific amount of time, the memory device sends the information to the memory controller. According to an embodiment, “dummy” data is sent first prior to the availability of the data read out of the memory devices, while waiting for the requested data to be accessed, and then the actual data is sent immediately following the dummy data. According to an embodiment, a geometry of a memory device has only one column of memory cells that are used to store information.

Abstract: An integrated circuit system, and a method of operation thereof, including: a memory unit having a volatile memory device with data and a non-volatile controller unit; a memory unit controller of the non-volatile controller unit for receiving a snoop signal for indicating an error; a non-volatile device of the memory unit for synchronously receiving data of the volatile memory device based on the snoop signal, the data autonomously copied without any intervention from outside the memory unit to prevent loss of the data; and an in-band command received by the memory unit, for autonomously restoring the data to the volatile memory device from the non-volatile device without any intervention from outside the memory unit.

Abstract: A method of manufacture of the memory management system includes: fabricating a dual in-line memory module carrier; mounting a volatile memory device on the dual in-line memory module carrier; mounting a non-volatile memory on the dual in-line memory module carrier on a side opposite the volatile memory device; mounting an uninterruptible power supply on the dual in-line memory module carrier for maintaining a memory module power when a system power input decays; and mounting a controller logic integrated circuit on the dual in-line memory module carrier coupled to the volatile memory device, the non-volatile memory, and the uninterruptible power supply for copying data content of the volatile memory device to the non-volatile memory when the uninterruptible power supply detects the decay of the system power input to a first cross-over level.