Abstract: According to one embodiment, an information processing apparatus is allowed to access a storage device storing time-series data generated by a first device. The information processing apparatus includes a processor holding a first public key and a first private key. The processor is configured to acquire a program for correcting an error in first data on a first product from a first entity. The processor is configured to correct the correction target first data, using data in a predetermined range of the time-series data. The processor is configured to generate ground data indicating correction grounds for the corrected correction target first data, based on the data in the predetermined range, and add the ground data to the corrected correction target first data.

Abstract: A display driver comprises a touch controller configured to perform touch sensing on a display panel during a vertical sync period. A first field of the vertical sync period comprises a display period and a touch sensing period following the display period. A start timing of the touch sensing period is controlled by an internal clock signal. A first counter is configured to, responsive to completion of the touch sensing, start a counting operation in synchronization with the internal clock signal. Gate control signal generator circuitry is configured to control a gate driver that is configured to drive a plurality of gate lines of the display panel. A gate line that is to be driven first to a high level during a second field following the first field is driven to the high level responsive to a count value of the first counter during the first field.

Abstract: A display driver comprises drop amount calculation circuitry and digital gamma correction circuitry. The drop amount calculation circuitry is configured to calculate a drop amount of a power source voltage supplied to a display panel from a setting value. The digital gamma correction circuitry is configured to perform digital gamma correction on an input image data based on the drop amount.

Abstract: A processing system comprises interface circuitry and a timing controller. The interface circuitry is configured to receive a vertical sync period indicator that indicates a start of an external vertical sync period. The timing controller is configured to, in response to a change in a display frame rate, control timing of a display drive operation and a proximity sensing operation to maintain a proximity sensing frame rate based on input timing of the vertical sync period indicator to the interface circuitry. The processing system is configured to supply drive signals to display elements of a display panel in the display drive operation and acquire sensing signals from sensor electrodes of the display panel in the proximity sensing operation.

Abstract: A processing system comprises interface circuitry and a timing controller. The interface circuitry is configured to receive a vertical sync period indicator that indicates a start of an external vertical sync period. The timing controller is configured to, in response to a change in a display frame rate, control timing of a display drive operation and a proximity sensing operation to maintain a proximity sensing frame rate based on input timing of the vertical sync period indicator to the interface circuitry. The processing system is configured to supply drive signals to display elements of a display panel in the display drive operation and acquire sensing signals from sensor electrodes of the display panel in the proximity sensing operation.

Abstract: A display driver comprises a touch controller configured to perform touch sensing on a display panel during a vertical sync period. A first field of the vertical sync period comprises a display period and a touch sensing period following the display period. A start timing of the touch sensing period is controlled by an internal clock signal. A first counter is configured to, responsive to completion of the touch sensing, start a counting operation in synchronization with the internal clock signal. Gate control signal generator circuitry is configured to control a gate driver that is configured to drive a plurality of gate lines of the display panel. A gate line that is to be driven first to a high level during a second field following the first field is driven to the high level responsive to a count value of the first counter during the first field.

Abstract: A display driver comprises a touch controller configured to perform touch sensing on a display panel during a vertical sync period. A first field of the vertical sync period comprises a display period and a touch sensing period following the display period. A start timing of the touch sensing period is controlled by an internal clock signal. A first counter is configured to, responsive to completion of the touch sensing, start a counting operation in synchronization with the internal clock signal. Gate control signal generator circuitry is configured to control a gate driver that is configured to drive a plurality of gate lines of the display panel. A gate line that is to be driven first to a high level during a second field following the first field is driven to the high level responsive to a count value of the first counter during the first field.

Abstract: A display driver includes: a memory comprising a plurality of memory regions each configured to store image data for one line of an image displayed in a frame; and control circuitry configured to adjust a number of in-use memory regions of the plurality of memory regions used to store the image data. The control circuitry is further configured to control the memory so that image data for respective lines of the image are cyclically stored in the in-use memory regions in a fixed order.

Abstract: A display driver comprises drop amount calculation circuitry and digital gamma correction circuitry. The drop amount calculation circuitry is configured to calculate a drop amount of a power source voltage supplied to a display panel from a setting value. The digital gamma correction circuitry is configured to perform digital gamma correction on an input image data based on the drop amount.

Abstract: A display driver comprises a touch controller configured to perform touch sensing on a display panel during a vertical sync period. A first field of the vertical sync period comprises a display period and a touch sensing period following the display period. A start timing of the touch sensing period is controlled by an internal clock signal. A first counter is configured to, responsive to completion of the touch sensing, start a counting operation in synchronization with the internal clock signal. Gate control signal generator circuitry is configured to control a gate driver that is configured to drive a plurality of gate lines of the display panel. A gate line that is to be driven first to a high level during a second field following the first field is driven to the high level responsive to a count value of the first counter during the first field.

Abstract: A display driver includes: a memory comprising a plurality of memory regions each configured to store image data for one line of an image displayed in a frame; and control circuitry configured to adjust a number of in-use memory regions of the plurality of memory regions used to store the image data. The control circuitry is further configured to control the memory so that image data for respective lines of the image are cyclically stored in the in-use memory regions in a fixed order.

Abstract: The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.

Abstract: The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.

Abstract: The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.

Abstract: The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.

Abstract: The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.

Abstract: The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.

Abstract: A level converter level-converts an oscillation output signal of a reference frequency oscillator and supplies the level-converted signal to a phase comparator of a PLL/fractional synthesizer for controlling an oscillation frequency of an RF transmission voltage-controlled oscillator. The level converter includes a self-bias type voltage amplifier which amplifies a reference frequency signal of the reference frequency oscillator. The self-bias type voltage amplifier includes a coupling capacitor, an amplifying transistor, a load and a bias element and suppresses a variation in the level of each harmonic component even though an external power supply voltage varies.

Abstract: A level converter level-converts an oscillation output signal of a reference frequency oscillator and supplies the level-converted signal to a phase comparator of a PLL/fractional synthesizer for controlling an oscillation frequency of an RF transmission voltage-controlled oscillator. The level converter includes a self-bias type voltage amplifier which amplifies a reference frequency signal of the reference frequency oscillator. The self-bias type voltage amplifier includes a coupling capacitor, an amplifying transistor, a load and a bias element and suppresses a variation in the level of each harmonic component even though an external power supply voltage varies.